Method of forming MOS and bipolar transistors

Abstract

Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

What is claimed is: 
     
       1. A method of forming a vertical bipolar transistor and a MOS transistor supported by a substrate including a semiconductor layer arranged on an insulating layer covering a semiconductor substrate doped with a first conductivity type, comprising the steps of:
 for the vertical bipolar transistor:
 a) etching an opening extending through the insulating region; 
 b) epitaxially growing a first epitaxial portion from the semiconductor substrate which fills the opening; and 
 c) doping the first epitaxial portion and a portion of the semiconductor substrate with a second conductivity type; 
 
 for the MOS transistor:
 d) forming a transistor gate extending over the semiconductor layer; and 
 
 for both the vertical bipolar transistor and the MOS transistor:
 e) epitaxially growing second epitaxial portions from both the semiconductor layer and the first epitaxial portion; 
 
 wherein the second epitaxial portion over the first epitaxial portion forms an emitter of the bipolar transistor and wherein the second epitaxial portions on each side of the transistor gate form source and drain regions of the MOS transistor. 
 
     
     
       2. The method of  claim 1 , further comprising:
 doping the second epitaxial portion over the first epitaxial portion with the first conductivity type; and 
 doping the second epitaxial portions on each side of the transistor gate with the second conductivity type. 
 
     
     
       3. The method of  claim 1 , further comprising, for the vertical bipolar transistor, removing the semiconductor layer. 
     
     
       4. The method of  claim 1 , further comprising forming a trench isolation between a region for the MOS transistor and a region for the vertical bipolar transistor. 
     
     
       5. The method of  claim 4 , wherein d) forming a transistor gate further comprises forming a further transistor gate extending on top of the trench isolation. 
     
     
       6. The method of  claim 1 , wherein the doped first epitaxial portion and portion of the semiconductor substrate form a base of the vertical bipolar transistor and wherein the semiconductor substrate forms a collector of the vertical bipolar transistor. 
     
     
       7. The method of  claim 1 , wherein the semiconductor layer is made of silicon. 
     
     
       8. The method of  claim 1 , wherein the semiconductor layer has a thickness smaller than 20 nm. 
     
     
       9. An integrated circuit, comprising:
 a substrate including a semiconductor layer arranged on an insulating layer covering a semiconductor substrate doped with a first conductivity type; 
 a trench isolation separating a first region of the substrate from a second region of the substrate, wherein the second region does not include the semiconductor layer; 
 wherein the substrate in the second region includes an opening extending through the insulating layer; 
 first epitaxial material filling the opening to form a base of a bipolar transistor having a collector formed by at least a portion of said semiconductor substrate; 
 a transistor gate extending over the semiconductor layer; 
 second epitaxial material over the first epitaxial portion and over the semiconductor layer on each side of the transistor gate; 
 wherein the second epitaxial material over the first epitaxial portion forms an emitter of the bipolar transistor and wherein the second epitaxial material on each side of the transistor gate form source and drain regions of a MOS transistor. 
 
     
     
       10. The integrated circuit of  claim 9 , wherein the second epitaxial material over the first epitaxial portion is doped with the first conductivity type, and wherein the second epitaxial material on each side of the transistor gate is doped with the second conductivity type. 
     
     
       11. The integrated circuit of  claim 9 , further comprising a further transistor gate extending on top of the trench isolation. 
     
     
       12. The integrated circuit of  claim 9 , wherein the semiconductor layer is made of silicon. 
     
     
       13. The integrated circuit of  claim 9 , wherein the semiconductor layer has a thickness smaller than 20 nm.