Semiconductor structure and manufacturing method thereof

Abstract

The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

What is claimed is: 
     
       1. A method for forming a semiconductor structure, comprising:
 providing a substrate; 
 forming an interlayer dielectric (ILD) on the substrate; 
 forming a first dummy gate in the ILD, wherein the first dummy gate comprises a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively; 
 forming two contact holes in the ILD at two sides of the first dummy gate respectively; 
 removing the dummy gate electrode, so as to form a gate recess in the ILD; 
 filling a first material layer in the gate recess and a second material layer in the two contact holes respectively; and 
 performing an anneal process on the two spacers, to bend the two spacers into two inward curving spacers. 
 
     
     
       2. The method of  claim 1 , wherein the first material layer includes a spin-on dielectric (SOD) layer. 
     
     
       3. The method of  claim 1 , wherein the second material layer includes an advanced patterning film (APF). 
     
     
       4. The method of  claim 1 , further comprising removing the first material layer and the second material layer after the two inward curving spacers are formed. 
     
     
       5. The method of  claim 4 , further comprising forming a first gate dielectric layer and a first electrode between the two inward curving spacers, so as to form a first gate structure. 
     
     
       6. The method of  claim 5 , wherein the anneal process is performed after the first gate dielectric layer is formed. 
     
     
       7. The method of  claim 5 , wherein the first gate structure is an N-type metal oxide semiconductor field effect transistor (NMOSFET). 
     
     
       8. The method of  claim 4 , further comprising forming a conductive layer in the two contact holes after the second material layer is removed. 
     
     
       9. The method of  claim 1 , further comprising forming a second gate structure, wherein the second gate structure comprises a second gate electrode and two outward curving spacers disposed on two sides of the gate electrode. 
     
     
       10. The method of  claim 9 , wherein the second gate structure is a P-type metal oxide semiconductor field effect transistor (PMOSFET). 
     
     
       11. The method of  claim 1 , wherein each spacer is disposed between and directly contacts the first material layer and the second material layer. 
     
     
       12. The method of  claim 1 , wherein the anneal process is performed after the first material layer and the second material layer are formed.