Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication

Abstract

A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.

What is claimed is: 
     
       1. A method of fabricating a static random access memory (SRAM) device, comprising:
 forming a plurality of fin structures over a substrate; 
 forming a plurality of gate stacks over the substrate, wherein side surfaces of the gate stacks are surrounded by a dielectric structure, and wherein the gate stacks are formed to each wrap around a top surface and side surfaces of the fin structures; 
 forming a plurality of contact-line-blocking patterns over the dielectric structure, wherein the contact-line-blocking patterns are formed using three or more lithography masks; 
 forming a plurality of trenches in the dielectric structure, wherein the contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns; and 
 filling the trenches with a conductive material to form a plurality of contact lines of the SRAM device. 
 
     
     
       2. The method of  claim 1 , wherein the forming of the contact-line-blocking patterns comprises:
 forming a first contact-line-blocking pattern using a first lithography mask that includes a first mask pattern; 
 forming a second contact-line-blocking pattern using a second lithography mask that includes a second mask pattern; and 
 forming a third contact-line-blocking pattern using a third lithography mask that includes a third mask pattern. 
 
     
     
       3. The method of  claim 2 , wherein the forming the plurality of trenches comprises etching a first trench for a first Vcc contact and a second trench for a first Vss contact, and wherein a portion of the dielectric structure disposed below the first contact-line-blocking pattern and between the first trench and the second trench is unetched. 
     
     
       4. The method of  claim 2 , wherein the forming the plurality of trenches comprises etching a third trench for a second Vcc contact and a fourth trench for a first bit-line contact, and wherein a portion of the dielectric structure disposed below the second contact-line-blocking pattern and between the third trench and the fourth trench is unetched. 
     
     
       5. The method of  claim 2 , wherein the forming the plurality of trenches comprises etching a fifth trench for a first node contact and a sixth trench for a second node contact, and wherein a portion of the dielectric structure disposed below the third contact-line-blocking pattern and between the fifth trench and the sixth trench is unetched. 
     
     
       6. The method of  claim 1 , wherein the forming the plurality of contact-line-blocking patterns comprises: implanting dopants into a plurality of portion of a silicon layer formed over the dielectric structure, thereby forming a plurality of doped portions of the silicon layer, wherein each of the doped portions is defined using a respective one of the three or more lithography masks. 
     
     
       7. The method of  claim 1 , wherein each of the contact-line-blocking patterns is defined by a respective rectangular mask pattern. 
     
     
       8. The method of  claim 1 , wherein:
 the gate stacks are formed over the substrate in a vertical direction; and 
 side surfaces of the gate stacks are surrounded in a horizontal direction by the dielectric structure. 
 
     
     
       9. A method of fabricating a static random access memory (SRAM) device, comprising:
 forming a plurality of gate structures, wherein each of the gate structures is embedded in an interlayer dielectric (ILD) and wraps around one or more semiconductor fin structures; 
 forming a hard mask layer over the ILD; 
 forming a silicon layer over the hard mask layer; 
 forming one or more first doped components in the silicon layer, wherein the one or more first doped components are defined by a first lithography mask; 
 forming one or more second doped components in the silicon layer, wherein the one or more second doped components are defined by a second lithography mask different from the first lithography mask; 
 forming one or more third doped components in the silicon layer, wherein the one or more third doped components are defined by a third lithography mask different from the first lithography mask and the second lithography mask; 
 removing undoped portions of the silicon layer; 
 patterning the hard mask layer to define a plurality of trenches in the hard mask layer, wherein the one or more first, second, and third doped components in the silicon layer prevent trench lines from being formed thereunder; 
 etching the trenches into the ILD; and 
 filling the trenches in the ILD with a metal material to form a plurality of contacts of the SRAM device. 
 
     
     
       10. The method of  claim 9 , wherein the patterning comprising defining at least a first discontinuous trench, a second discontinuous trench, and a third discontinuous trench for each SRAM cell of the SRAM device. 
     
     
       11. The method of  claim 10 , wherein the first discontinuous trench includes trench segments that, after being etched into the ILD and filled with the metal material, form a bit-line contact, a Vcc contact, and a Vss contact. 
     
     
       12. The method of  claim 11 , wherein:
 the second discontinuous trench includes trench segments that, after being etched into the ILD and filled with the metal material, form a first node contact and a second node contact; and 
 the third discontinuous trench includes trench segments that, after being etched into the ILD and filled with the metal material, form a Vss contact, a Vcc contact, and a bit-line contact. 
 
     
     
       13. A method of fabricating a static random access memory (SRAM) device, comprising:
 forming a plurality of gate structures a substrate, wherein the gate structures are surrounded by an interlayer dielectric (ILD); 
 forming a layer over the gate structures and over the ILD; 
 forming a plurality of blocking patterns by doping different portions of the layer; 
 etching a plurality of trenches in the ILD, wherein the blocking patterns prevent portions of the ILD underneath from being etched; and 
 filling the trenches with a conductive material. 
 
     
     
       14. The method of  claim 13 , wherein the forming the layer comprises forming a silicon layer over the ILD. 
     
     
       15. The method of  claim 14 , wherein the forming the blocking patterns comprises doping different portions of the silicon layer with boron, wherein the different portions are separated from one another in a top view. 
     
     
       16. The method of  claim 13 , wherein the forming the blocking patterns comprises using a plurality of lithography masks. 
     
     
       17. The method of  claim 13 , wherein:
 the trenches each extend in a first direction in a top view; and 
 the blocking patterns each extend in a second direction different from the first direction in a top view. 
 
     
     
       18. The method of  claim 13 , wherein:
 the etching comprises etching a Vcc contact trench and a Vss contact trench of the SRAM device; and 
 one of the blocking patterns is located between the Vcc contact trench and the Vss contact trench in a top view. 
 
     
     
       19. The method of  claim 13 , wherein:
 the etching comprises etching a Vcc contact trench and a bit-line contact trench of the SRAM device; and 
 one of the blocking patterns is located between the Vcc contact trench and the bit-line contact trench in a top view. 
 
     
     
       20. The method of  claim 13 , wherein:
 the etching comprises etching a first node contact trench and a second node contact trench of the SRAM device; and 
 one of the blocking patterns is located between the first node contact trench and the second node contact trench in a top view.