Built-in self test for A/D converter

Abstract

Analog-to-digital conversion is tested in-field using an on-chip built-in self-test (BIST) sub-circuit formed within an underlying integrated circuit. Processing cycles may be conscripted during an idle state when the analog-to-digital conversion is not needed. The BIST requires a test time which may be compared to an idle time. If the idle time exceeds the test time, then the BIST may be entirely performed. However, if the idle time is unknown or less than the test time, the BIST may be paused and resumed between subsequent idle states.

What is claimed is: 
     
       1. A method, comprising:
 determining a first idle state of an analog-to-digital converter during normal operation; 
 initiating a built-in self-test operation to test the analog-to-digital converter during the first idle state; 
 providing built-in self-test test data to the analog-to-digital converter during the first idle state in response to the initiating of the built-in self-test operation; 
 analyzing a test result produced by the analog-to-digital converter based on the test data; 
 determining a second idle state of the analog-to-digital converter during normal operation; 
 initiating a second built-in self-test operation to test the analog-to-digital converter during the second idle state; and 
 interrupting the second built-in self-test operation, prior to completing the second built-in self-test operation, in response to a resumption of an analog-to-digital conversion performed by the analog-to-digital converter during normal operation. 
 
     
     
       2. The method of  claim 1 , wherein analyzing the test results includes determining the analog-to-digital converter passed the built-in self-test operation based on the test result matching an expected test result. 
     
     
       3. The method of  claim 1 , wherein analyzing the test results includes determining the analog-to-digital converter failed the built-in self-test operation based on the test result not matching an expected test result. 
     
     
       4. The method of  claim 1 , further comprising saving a state of the second built-in self-test operation in response to the interrupting of the second built-in self-test operation. 
     
     
       5. The method of  claim 4 , further comprising resuming the second built-in self-test operation of the analog-to-digital converter after saving the state. 
     
     
       6. The method of  claim 1 , further comprising aborting the second built-in self-test operation in response to the interrupting of the second built-in self-test operation. 
     
     
       7. A method, comprising:
 determining, at a first time, an idle state in analog-to-digital conversion performed by an analog-to-digital converter during normal operation; 
 determining a test time for a built-in self-test operation of the analog-to-digital converter in response to the idle state in the analog-to-digital conversion; 
 determining an idle time of the idle state in the analog-to-digital conversion performed by the analog-to-digital converter; 
 initiating the built-in self-test operation of the analog-to-digital converter in response to the idle time at least equaling the test time; 
 providing built-in self-test test data to the analog-to-digital converter in response to the initiating of the built-in self-test operation; 
 analyzing a test result produced by the analog-to-digital converter based on the test data; 
 determining at a second time, a second idle state in analog-to-digital conversion performed by an analog-to-digital converter during normal operation; 
 initiating a second built-in self-test operation to test the analog-to-digital converter during the second idle state; and 
 interrupting the second built-in self-test operation, prior to completing the second built-in self-test operation, in response to a resumption of an analog-to-digital conversion performed by the analog-to-digital converter during normal operation. 
 
     
     
       8. The method of  claim 7 , further comprising determining the analog-to-digital converter passed the built-in self-test operation based on the test result. 
     
     
       9. The method of  claim 7 , further comprising determining the analog-to-digital converter failed the built-in self-test operation based on the test result. 
     
     
       10. The method of  claim 7 , further comprising saving a state of the second built-in self-test operation in response to the interrupting. 
     
     
       11. The method of  claim 7 , further comprising resuming the second built-in self-test operation of the analog-to-digital converter after the interrupting. 
     
     
       12. The method of  claim 7 , further comprising aborting the second built-in self-test operation in response to the interrupting of the built-in self-test operation. 
     
     
       13. A device, comprising:
 an analog-to-digital converter at a substrate; 
 built-in self-test state detection circuitry at the substrate configured to determine an idle state in analog-to-digital conversion performed by the analog-to-digital converter during normal operation; 
 a built-in self-test controller circuitry configured to initiate a built-in self-test operation by the device of the analog-to-digital converter in response to the built-in self-test detection circuitry determining the occurrence of the idle state; 
 a built-in self-test signal generator circuitry configured to provide an analog test signal to the analog-to-digital converter in response to the built-in self-test controller circuitry initiating the built-in self-test operation; 
 a built-in self-test performance circuitry configured to analyze a test result produced by the analog-to-digital converter 
 wherein the built-in self-test controller circuitry is further configured to interrupt the built-in self-test operation, prior to completing the built-in self-test operation, in response to a resumption of an analog-to-digital conversion performed by the analog-to-digital converter during normal operation. 
 
     
     
       14. The device of  claim 13 , wherein the built-in self-test controller circuitry further configured to determine that the analog-to-digital converter passed the built-in self-test operation based on the test result. 
     
     
       15. The device of  claim 13 , wherein the built-in self-test controller circuitry further configured to determine that the analog-to-digital converter failed the built-in self-test operation based on the test result. 
     
     
       16. The device of  claim 13 , wherein the built-in self-test controller circuitry is further configured to determine that an idle time of the idle state exceeds a test time of the built-in self-test operation prior to initiating the built-in self-test operation. 
     
     
       17. The device of  claim 13 , wherein the built-in self-test controller circuitry is to complete the built-in self-test operation of the analog-to-digital converter within the idle time.