Electrical circuits and methods to correct duty cycle error

Abstract

Electrical circuits and associated methods relate to duty cycle correction having a voltage controlled delay line VCDL controlled by an analog voltage and a digital command signal to generate a VCDL out signal. In an illustrative example, the analog voltage may be generated by an analog circuit, the analog circuit may include a reference voltage, a low-pass filter, an amplifier and a loop filter. In an illustrative example, the analog circuit may be controlled by an analog command signal. The analog command signal may be programmable applied on the analog circuit to produce the analog voltage. The digital command signal may be programmable to select desired delay band in the VCDL. The analog voltage and the digital command signal may be applied to the VCDL together to obtain a desired duty cycle.

What is claimed is: 
     
       1. An electrical circuit, comprising:
 a low-pass filter (LPF) receiving an output clock signal from a logic circuit; 
 an amplifier configured to generate a first analog signal in response to an analog command signal and an output signal from the LPF; 
 a loop filter configured to generate a second analog signal in response to the first analog signal from the amplifier; and, 
 a reset logic circuit, in response to an external reset signal and an output VCDL out  signal of a voltage controlled delay line VCDL, configured to generate a final reset signal to reset the logic circuit, 
 wherein, the VCDL is configured to generate the VCDL out  signal in response to the second analog signal and a digital command signal. 
 
     
     
       2. The electrical circuit of  claim 1 , wherein, after resetting the logic circuit, a duty cycle of the output clock signal becomes about 50%. 
     
     
       3. The electrical circuit of  claim 1 , wherein the VCDL is configured to select a delay range in response to a digital command signal. 
     
     
       4. The electrical circuit of  claim 3 , wherein the VCDL is further configured to adjust an amount of delay to correct a duty cycle error of the output clock signal in response to the analog command signal. 
     
     
       5. The electrical circuit of  claim 1 , wherein the VCDL further comprises a plurality of cascaded stages, each of the plurality of cascaded stages comprising a plurality of delay buffers. 
     
     
       6. The electrical circuit of  claim 5 , wherein each of the plurality of delay buffers further comprises:
 a PMOS transistor and a NMOS transistor arranged as a CMOS inverter; 
 an NMOS transistor electrically connected with the NMOS transistor in series; and, 
 a plurality of digital controlled delay bands coupled to an output of the CMOS inverter, 
 wherein the NMOS transistor is configured to present a controllable resistance in response to the second analog signal. 
 
     
     
       7. The electrical circuit of  claim 6 , wherein each of the plurality of delay buffers further comprises an NMOS transistor in parallel with the NMOS transistor, and the NMOS transistor is coupled to a high input voltage V dd . 
     
     
       8. The electrical circuit of  claim 6 , wherein each of the plurality of digital controlled delay bands comprises a plurality of slices configured in parallel, wherein each of the plurality of slices is configured to be selectively enabled in response to the digital command signal. 
     
     
       9. The electrical circuit of  claim 1 , wherein the reset logic comprises:
 at least one inverter configured to invert and delay the VCDL out  signal; 
 a first NAND gate configured to generate an internal reset signal in response to the VCDL out  signal and the inverted and delayed VCDL out  γ signal; 
 a second inverter configured to invert the external reset signal; and, 
 a second NAND gate configured to generate the final reset signal in response to the internal reset signal and the inverted external reset signal. 
 
     
     
       10. The electrical circuit of  claim 1 , wherein the logic circuit comprises a D-type flip flop, and the amplifier comprises an operational transconductance amplifier OTA. 
     
     
       11. A method to correct duty cycle error, comprising:
 sending an output clock signal from a logic circuit to a low-pass filter (LPF) and a voltage-controlled delay line (VCDL); 
 generating a first analog signal in response to an analog command signal and an output signal from the LPF; 
 transferring the first analog signal into a second analog signal through a loop filter; 
 generating an output VCDL out  signal by the VCDL in response to the second analog signal and a digital command signal; 
 generating a final reset signal resetting the logic circuit in response to an external reset signal and the VCDL out  signal. 
 
     
     
       12. The method of  claim 11 , wherein, after resetting the logic circuit, a duty cycle of the output clock signal becomes about 50%. 
     
     
       13. The method of  claim 11 , wherein the VCDL is configured to select a delay range in response to a digital command signal. 
     
     
       14. The method of  claim 13 , wherein the VCDL is further configured to adjust an amount of delay to correct a duty cycle error of the output clock signal in response to the analog command signal. 
     
     
       15. The method of  claim 11 , wherein the VCDL further comprises a plurality of cascaded stages, each of the plurality of cascaded stages comprising a plurality of delay buffers. 
     
     
       16. The method of  claim 15 , wherein each of the plurality of delay buffers further comprises:
 a PMOS transistor and an NMOS transistor arranged as a CMOS inverter; 
 an NMOS transistor connected with the NMOS transistor in series; and, 
 a plurality of digital controlled delay bands coupled to an output of the CMOS inverter, 
 wherein the NMOS transistor is configured to present a controllable resistance in response to the second analog signal. 
 
     
     
       17. The method of  claim 16 , wherein each of the plurality of delay buffers further comprises an NMOS transistor in parallel with the NMOS transistor, and the NMOS transistor is coupled to a high input voltage V dd . 
     
     
       18. The method of  claim 16 , wherein each of the plurality of digital controlled delay bands comprises a plurality of slices configured in parallel, wherein each of the plurality of slices is configured to be selectively enabled in response to the digital command signal. 
     
     
       19. The method of  claim 11 , wherein the final reset signal is generated by a reset logic circuit, the reset logic circuit comprises:
 an inverter configured to invert the VCDL out  signal; 
 a first NAND gate is configured to generate an output signal in response to the VCDL out  signal and the inverted VCDL out  signal; 
 a second inverter configured to generate the external reset signal; and, 
 a second NAND gate configured to generate the reset final signal in response to the first NAND gate output signal and the inverted external reset signal. 
 
     
     
       20. The method of  claim 11 , wherein the logic circuit comprises a D-type flip flop.