Interface for non-volatile memory

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. The set of ports includes a first port and a second port. The first port includes a first plurality of electrical contacts and the second port includes a second plurality of electrical contacts. The on-die controller communicates via the set of ports to receive command and address information and to transfer data for a data operation on the array of non-volatile memory cells. The on-die controller uses the first port and the second port in a first mode and uses the first port without the second port in a second mode. The second mode provides compatibility with an interface of a legacy type of memory die.

What is claimed is: 
     
       1. An apparatus comprising:
 one or more memory die, a memory die comprising:
 an array of non-volatile memory cells; 
 a set of ports, the set of ports comprising a first port and a second port, the first port comprising a first plurality of electrical contacts and the second port comprising a second plurality of electrical contacts; and 
 an on-die controller configured to communicate via the first port and the second port to receive command and address information and to transfer data for data operations on the array of non-volatile memory cells, the on-die controller using the first port to receive command and address information and the second port to transfer data in a first mode and using the first port to receive command and address information and to transfer data while the second port is inactive in a second mode, the second mode providing compatibility with an interface of a legacy type of memory die. 
 
 
     
     
       2. The apparatus of  claim 1 , the first mode comprising a storage class memory interface wherein the on-die controller receives the command and address information via the first port, and transfers the data via the second port. 
     
     
       3. The apparatus of  claim 1 , the second mode providing a NAND storage interface wherein the on-die controller both receives the command and address information and transfers the data via the first port. 
     
     
       4. The apparatus of  claim 1 , wherein the on-die controller uses at least one set of contacts of the set of ports for single-ended input/output, and uses at least one pair of contacts of the set of ports for a differential strobe. 
     
     
       5. The apparatus of  claim 1 , wherein the on-die controller receives the command and address information according to a command and address strobe signal received via one or more command and address strobe lines of the set of ports, and transfers the data according to a data strobe signal communicated via one or more data strobe lines of the set of ports, the command and address strobe signal independent from the data strobe signal. 
     
     
       6. The apparatus of  claim 5  wherein the command and address strobe signal is inactive except when the on-die controller receives command and address information, and the data strobe signal is inactive except when the on-die controller transfers data. 
     
     
       7. The apparatus of  claim 5 , further comprising a device controller that:
 sends the command and address information and the command and address strobe signal; 
 for a write operation, sends the data and the data strobe signal; and 
 for a read operation, sends a read enable clock signal and receives the data and the data strobe signal, the data strobe signal sent by the on-die controller based on the read enable clock signal. 
 
     
     
       8. The apparatus of  claim 7 , wherein the device controller generates one or more of the command and address strobe signal, the read enable clock signal, and the data strobe signal without sending a free-running clock signal to the one or more memory die. 
     
     
       9. The apparatus of  claim 7 , wherein the device controller sends one of the data strobe signal and the read enable clock signal in response to waiting a latency time after initiating the command and address strobe signal for a data operation. 
     
     
       10. The apparatus of  claim 7 , wherein the device controller waits at least a gap time between sending the command and address information for a data operation and sending command and address information for a subsequent data operation. 
     
     
       11. The apparatus of  claim 7 , wherein the device controller waits at least a predefined preamble time between sending an enable signal and sending one or more of the command and address strobe signal, the read enable clock signal, and the data strobe signal. 
     
     
       12. The apparatus of  claim 1 , wherein the on-die controller queues a plurality of commands at an input stage of a command queue, services a command from an output stage of the command queue in response to a burst of clock pulses from a device controller, and provides an end of burst signal to the command queue to shift the output stage of the command queue to a subsequent command in response to a count of the clock pulses satisfying a threshold. 
     
     
       13. An apparatus comprising:
 a memory die comprising:
 an array of non-volatile memory cells; 
 a first port and a second port; and 
 a controller configured to:
 use the first port to receive command and address information and the second port to transfer data in a first mode, and use the first port to receive command and address information and to transfer data while the second port is inactive in a second mode; 
 queue a plurality of commands, for data operations on the array of non-volatile memory cells, at an input stage of a command queue; 
 service a command from an output stage of the command queue in response to a series of clock pulses from a device controller; and 
 shift the output stage of the command queue to a subsequent command in response to a count of the clock pulses satisfying a threshold. 
 
 
 
     
     
       14. The apparatus of  claim 13 , wherein the controller comprises a synchronizer that counts the clock pulses and adds an end of series indicator to the command queue in response to the count of the clock pulses satisfying the threshold, wherein shifting the output stage of the command queue is in response to the end of series indicator. 
     
     
       15. The apparatus of  claim 13 , wherein the controller comprises a first command queue for queuing read commands and a second command queue for queuing write commands. 
     
     
       16. The apparatus of  claim 13 , wherein the controller enables one or more input/output lines based on the command from the output stage of the command queue. 
     
     
       17. The apparatus of  claim 16 , wherein the command from the output stage of the command queue is a read command and the controller enables one or more input/output lines for receiving a read enable clock signal and for sending data and data strobe pulses, and disables one or more input/output lines for receiving write data and data strobe pulses, in response to the read command. 
     
     
       18. The apparatus of  claim 16 , wherein the command from the output stage of the command queue is a write command and the controller enables one or more input/output lines for receiving write data and data strobe pulses, and disables one or more input/output lines for receiving a read enable clock signal and for sending data and data strobe pulses, in response to the write command. 
     
     
       19. A system comprising:
 one or more memory die, a memory die comprising:
 an array of non-volatile memory cells; 
 a set of ports, the set of ports comprising a first port and a second port, the first port comprising a first plurality of electrical contacts and the second port comprising a second plurality of electrical contacts; and 
 an on-die controller that queues a plurality of commands at an input stage of a command queue, services a command from an output stage of the command queue in response to a burst of clock pulses from a device controller, and shifts the output stage of the command queue to a subsequent command in response to a count of the clock pulses satisfying a threshold; and 
 a device controller that communicates with the on-die controller for a selected die via the first port and the second port to send command and address information and to transfer data for data operations on the selected die, wherein the device controller uses the first port for command and address information and the second port for data in a first mode, and uses the first port for command and address information and data while not using the second port in a second mode, the second mode providing compatibility with an interface of a legacy type of memory die. 
 
 
     
     
       20. The system of  claim 19 , wherein:
 the first mode comprises a storage class memory interface wherein the device controller sends the command and address information via the first port, and transfers the data via the second port; and 
 the second mode comprises a NAND storage interface wherein the device controller both sends the command and address information and transfers the data via the first port.