Input buffer circuit

Abstract

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.

What is claimed is: 
     
       1. An apparatus comprising:
 a first amplifier configured to be activated by a first power supply voltage to provide a first intermediate voltage on a first node and a second intermediate voltage on a second node; 
 a voltage switch configured to be activated by one of first and second precharge voltages from a third node, the voltage switch coupled to a fourth node; and 
 a second amplifier comprising first and second inverters coupled to the fourth node, the second amplifier configured to be activated by a second power supply voltage from the voltage switch to provide an output voltage when the voltage switch is activated, responsive to the one of the first and second precharge voltages. 
 
     
     
       2. The apparatus of  claim 1 , wherein the first power supply voltage has a same voltage level as the second power supply voltage, and
 wherein the voltage switch is configured to provide the second power supply voltage to the second amplifier, responsive to one of the first intermediate voltage and the second intermediate voltage. 
 
     
     
       3. The apparatus of  claim 1 , further comprising another voltage switch coupled to the first amplifier and configured to provide the first power supply voltage to the first amplifier. 
     
     
       4. The apparatus of  claim 1 , wherein the first and second precharge voltages are provided to the third node responsive to, respectively, the first intermediate voltage on the first node and the second intermediate voltage on the second node. 
     
     
       5. The apparatus of  claim 1 , wherein the first amplifier includes a first transistor, and a second transistor coupled to the first transistor, and
 wherein the first and second transistors are coupled to the first and second nodes, respectively. 
 
     
     
       6. The apparatus of  claim 1 , further comprising:
 fifth and sixth transistors coupled to the first and second nodes, respectively; and 
 seventh and eighth transistors coupled to the fifth and sixth transistors, respectively. 
 
     
     
       7. The apparatus of  claim 1 , further comprising:
 a third transistor; and 
 a fourth transistor coupled to the third transistor, 
 wherein the third and fourth transistors are coupled to the first and second nodes, respectively. 
 
     
     
       8. The apparatus of  claim 7 , wherein one of the third and fourth transistors is configured to be turned on responsive to one of the first and second intermediate voltages, respectively. 
     
     
       9. The apparatus of  claim 1 , further comprising fifth and sixth transistors coupled to the first and second nodes, respectively. 
     
     
       10. The apparatus of  claim 9 , wherein the fifth and sixth transistors are configured to be turned on to increase voltages of a first output node and a second output node, respectively. 
     
     
       11. An apparatus comprising:
 a first amplifier comprising first and second transistors; 
 third and fourth transistors coupled to the first and second transistors, respectively; 
 a voltage switch coupled to the third and fourth transistors; and 
 a second amplifier coupled to the voltage switch, the second amplifier configured to be activated by the voltage switch to provide an output voltage when the voltage switch is activated. 
 
     
     
       12. The apparatus of  claim 11 , further comprising another voltage switch coupled to the first amplifier. 
     
     
       13. The apparatus of  claim 11 , wherein the first and second transistors are coupled to first and second nodes, respectively, and
 wherein the first amplifier is configured to be activated to provide one of first and second voltages on the first and second nodes, respectively. 
 
     
     
       14. The apparatus of  claim 11 , wherein the first and second transistors are configured to be turned on responsive to a data input signal and a reference voltage, respectively. 
     
     
       15. The apparatus of  claim 11 , further comprising fifth and sixth transistors coupled to the second amplifier. 
     
     
       16. The apparatus of  claim 11 , wherein the second amplifier comprises first and second inverters, and the first and second inverters are coupled to the voltage switch. 
     
     
       17. An apparatus comprising:
 a first amplifier comprising first and second transistors; 
 third and fourth transistors coupled to the first and second transistors, respectively; 
 a voltage switch coupled to the third and fourth transistors; 
 fifth and sixth transistors coupled to the third and fourth transistors, respectively; and 
 a second amplifier coupled to the voltage switch, the second amplifier configured to be activated by a power supply voltage from the voltage switch. 
 
     
     
       18. The apparatus of  claim 17 , wherein the fifth and sixth transistors are coupled to the first and second transistors, respectively, and the fifth and sixth transistors are configured to be turned on based on the first and second transistors, respectively. 
     
     
       19. The apparatus of  claim 17 , further comprising seventh and eighth transistors coupled to the third and fourth transistors, respectively, the seventh and eighth transistors further coupled to the fifth and sixth transistors, respectively. 
     
     
       20. The apparatus of  claim 19 , further comprising ninth and tenth transistors coupled to the fifth and sixth transistors, respectively.