Method of manufacturing embedded magnetoresistive random access memory

Abstract

A method of manufacturing an embedded magnetoresistive random access memory including the following steps is provided. A memory cell stack structure is formed on a substrate structure. The memory cell stack structure includes a first electrode, a second electrode, and a magnetic tunnel junction structure. A first dielectric layer covering the memory cell stack structure is formed. A metal nitride layer is formed on the first dielectric layer. A second dielectric layer is formed on the metal nitride layer. A first CMP process is performed on the second dielectric layer to expose the metal nitride layer by using the metal nitride layer as a stop layer. An etch back process is performed to completely remove the metal nitride layer and expose the first dielectric layer. A second CMP process is performed to expose the second electrode. The manufacturing method can have a better planarization effect.

What is claimed is: 
     
       1. A method of manufacturing an embedded magnetoresistive random access memory (eMRAM), comprising:
 forming a memory cell stack structure on a substrate structure, wherein the memory cell stack structure comprises: 
 a first electrode located on the substrate structure; 
 a second electrode located on the first electrode; and 
 a magnetic tunnel junction (MTJ) structure located between the first electrode and the second electrode; 
 forming a first dielectric layer covering the memory cell stack structure; 
 forming a metal nitride layer on the first dielectric layer; 
 forming a second dielectric layer on the metal nitride layer; 
 performing a first chemical mechanical polishing (CMP) process on the second dielectric layer to expose the metal nitride layer by using the metal nitride layer as a stop layer; 
 performing an etch back process to completely remove the metal nitride layer and expose the first dielectric layer; and 
 performing a second CMP process to expose the second electrode, wherein an embedded memory region and a device region adjacent to each other are defined in the substrate structure, the memory cell stack structure is located in the embedded memory region, and 
 before performing the first CMP process, 
 a height of the first dielectric layer in the embedded memory region is higher than a height of the first dielectric layer in the device region, 
 a height of the metal nitride layer in the embedded memory region is higher than a height of the metal nitride layer in the device region, and 
 a height of the second dielectric layer in the embedded memory region is higher than a height of the second dielectric layer in the device region. 
 
     
     
       2. The method of manufacturing the eMRAM according to  claim 1 , wherein the etch back process comprises a dry etching process with no selectivity. 
     
     
       3. The method of manufacturing the eMRAM according to  claim 1 , wherein the memory cell stack structure further comprises:
 a seed layer located between the first electrode and the MTJ structure. 
 
     
     
       4. The method of manufacturing the eMRAM according to  claim 1 , wherein the memory cell stack structure further comprises:
 a barrier layer located between the first electrode and the substrate structure. 
 
     
     
       5. The method of manufacturing the eMRAM according to  claim 1 , further comprising:
 forming a passivation layer covering the memory cell stack structure before forming the first dielectric layer. 
 
     
     
       6. The method of manufacturing the eMRAM according to  claim 1 , wherein a dielectric constant of the first dielectric layer and a dielectric constant of the second dielectric layer are different. 
     
     
       7. The method of manufacturing the eMRAM according to  claim 1 , wherein a material of the metal nitride layer comprises titanium nitride (TiN) or tantalum nitride (TaN). 
     
     
       8. The method of manufacturing the eMRAM according to  claim 1 , wherein a material of the second dielectric layer comprises a tetraethoxysilane (TEOS) oxide. 
     
     
       9. The method of manufacturing the eMRAM according to  claim 1 , further comprising:
 performing a wet cleaning process after performing the first CMP process and before performing the etch back process. 
 
     
     
       10. The method of manufacturing the eMRAM according to  claim 9 , wherein a cleaning solution of the wet cleaning process comprises ultra-dilute hydrofluoric acid (UDHF). 
     
     
       11. The method of manufacturing the eMRAM according to  claim 1 , further comprising:
 performing a wet cleaning process after performing the etch back process. 
 
     
     
       12. The method of manufacturing the eMRAM according to  claim 11 , wherein a cleaning solution of the wet cleaning process comprises UDHF. 
     
     
       13. The method of manufacturing the eMRAM according to  claim 1 , wherein after performing the first CMP process,
 the height of the metal nitride layer in the embedded memory region is higher than the height of the metal nitride layer in the device region, 
 the metal nitride layer in the embedded memory region is exposed, and 
 a portion of the second dielectric layer remains on the metal nitride layer in the device region. 
 
     
     
       14. The method of manufacturing the eMRAM according to  claim 13 , wherein the etch back process further removes the second dielectric layer remaining on the metal nitride layer and further removes a portion of the first dielectric layer. 
     
     
       15. The method of manufacturing the eMRAM according to  claim 13 , wherein after performing the etch back process,
 the height of the first dielectric layer in the embedded memory region and the height of the first dielectric layer in the device region are the same. 
 
     
     
       16. The method of manufacturing the eMRAM according to  claim 15 , wherein after performing the second CMP process,
 the height of the first dielectric layer in the embedded memory region and the height of the first dielectric layer in the device region are the same.