System for managing the wear of an electronic memory

Abstract

A system including: a first memory including several portions each of several pages, this memory including first and second ports that enable simultaneous access to two pages of distinct portions of the memory; and a control circuit suitable for implementing, via the second port, a method for balancing the wear of the memory, including movements of data within the memory, while authorizing simultaneous user access to the memory contents via the first port.

The invention claimed is: 
     
       1. A system comprising:
 a first resistive memory comprising a plurality of segments having a plurality of pages each, the first resistive memory comprising first and second memory ports configured to simultaneously access two pages of the first resistive memory that belong to different segments of the plurality of segments, each of said different segments comprising a single port of access to the pages in the respective segment, wherein the single ports can be connected to one or the other of the first and second memory ports of the first resistive memory via multiplexing circuits; and 
 a control circuit configured to implement, via the second memory port, a wear management method of managing wear of the first resistive memory, the wear management method comprising read and/or write accesses to data stored in the first resistive memory, while simultaneously allowing user accesses to content of the first resistive memory via the first memory port, the control circuit configured to access a particular segment of the first resistive memory for the wear management method only when no user access is being performed on the particular segment of the first resistive memory, 
 wherein the control circuit is configured to only access the particular segment of the first resistive memory for the wear management method simultaneously to user access of another segment of the first resistive memory. 
 
     
     
       2. The system of  claim 1 , wherein said wear management method comprises a wear balancing method comprising data displacements resulting in modifying a physical address of the data within the first resistive memory. 
     
     
       3. The system of  claim 1 , wherein the control circuit is configured to prioritize user accesses to the content of the first resistive memory over accesses of the wear management method. 
     
     
       4. The system of  claim 1 , comprising a counter or a table configured to provide to the control circuit information regarding which memory addresses are being processed by the wear management method. 
     
     
       5. The system of  claim 1 , wherein the control circuit is configured to only perform a write access to the particular segment of the first resistive memory for the wear management method simultaneously to a user write access to the another segment of the first resistive memory. 
     
     
       6. The system of  claim 1 , wherein the control circuit is configured to only perform a read access to the particular segment of the first resistive memory for the wear management method simultaneously to a user read access to the another segment of the first resistive memory. 
     
     
       7. The system of  claim 1 , further comprising first and second registers capable of each storing the content of a memory page. 
     
     
       8. The system of  claim 7 , further comprising first and second tables capable of each storing as many 2-bit entries as a memory portion comprises pages. 
     
     
       9. The system of  claim 7 , wherein, when data are displaced in the first resistive memory by the control circuit in the context of the wear management method, the data transit through the first and/or second registers and, when a user access targeting data contained in the first and/or second registers occurs, the control circuit processes this access in said registers. 
     
     
       10. The system of  claim 1 , further comprising second and third buffer memories capable of each storing the content of a segment of the first resistive memory. 
     
     
       11. The system of  claim 10 , further comprising first and second tables capable of each storing as many 1-bit entries as a segment of the first resistive memory comprises pages. 
     
     
       12. The system of  claim 10 , wherein, when data are displaced in the first resistive memory by the control circuit in the context of the wear management method, the data transit through the second and/or third buffer memories and, when a user access targeting data contained in the second and/or third buffer memories occurs, the control circuit processes this access in said second and third buffer memories. 
     
     
       13. The system of  claim 1 , further comprising a device capable of converting logic addresses, which are the addresses used by the user to access the content of the first resistive memory, into physical addresses, which are the addresses where the contents targeted by the user in the first resistive memory are effectively stored. 
     
     
       14. The system of  claim 13 , wherein the address conversion device comprises, for each segment of the first resistive memory, a counter or register for tracking the shifts of pages within the segment. 
     
     
       15. The system of  claim 1 , comprising a device for scrambling, by means of an encryption key, addresses used by the user to access the content of the first resistive memory. 
     
     
       16. The system of  claim 2 , wherein the data displacements of the wear balancing method are displacements internal to a single segment of the plurality of segments, or displacements between different segments of the plurality of segments. 
     
     
       17. The system of  claim 1 , wherein the wear management method comprises a wear measurement method comprising:
 a first reading from a target page, the wear of which is desired to be measured; 
 a second reading from said target page with a threshold of discrimination between binary values ‘0’ and ‘1’ modified with respect to the first step; and 
 a bit-to-bit comparison of the values read during the first reading and the second reading. 
 
     
     
       18. The system of  claim 1 , wherein the first resistive memory comprises a plurality of cells, each cell configured to be programmed in a highly resistive state and in a lightly resistive state, wherein the wear management method comprises a wear restore method comprising alternately writing and deleting, a plurality of times, into and from a memory cell deemed degraded, and/or resetting this cell by applying thereto a voltage of same biasing as a voltage normally used to program this cell to the lightly resistive state, but of greater value.