Semiconductor device and method

Abstract

Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.

I claim: 
     
       1. A method for forming a semiconductor package comprising:
 providing a first releasable chip carrier attached to a conductive layer; 
 forming a circuit layer on a surface of the conductive layer; 
 applying a dielectric layer over a surface of the circuit layer; 
 attaching a second releasable chip carrier to a surface of the dielectric layer; 
 releasing, by a first activating source, the first releasable chip carrier from the conductive layer; and 
 operationally testing circuitry of the circuit layer. 
 
     
     
       2. The method of  claim 1 , wherein results of said operationally testing indicate that the circuitry is operationally functional, and wherein said method further comprises:
 attaching a semiconductor die to portions of the circuit layer; 
 forming an encapsulating layer surrounding the semiconductor die; 
 attaching a third releasable chip carrier to a surface of the encapsulating layer; and 
 releasing, by a second activating source, the second releasable chip carrier from the surface of the dielectric layer. 
 
     
     
       3. The method of  claim 2 , wherein the first releasable chip carrier, the second releasable chip carrier, and the third releasable chip carrier each comprise a size format selected from the group consisting of a panel size format and a strip size format. 
     
     
       4. The method of  claim 2 , further comprising:
 removing portions of said dielectric layer thereby forming openings within the dielectric layer; and 
 forming ball grid array structures within the openings, wherein the ball grid array structures are electrically connected to the semiconductor die, and wherein the conductive layer, the circuit layer, the dielectric layer, the semiconductor die, the encapsulating layer, and the ball grid array structures form the semiconductor package. 
 
     
     
       5. The method of  claim 2 , wherein the second activating source comprises a same activating source as the first activating source. 
     
     
       6. The method of  claim 2 , wherein the second activating source differs from the first activating source. 
     
     
       7. The method of  claim 1 , wherein the first releasable chip carrier and the second releasable chip carrier each comprise a panel size format. 
     
     
       8. The method of  claim 1 , wherein the first releasable chip carrier comprises a panel size format, and wherein the second releasable chip carrier comprises a strip size format. 
     
     
       9. The method of  claim 1 , wherein the first activating source does not make physical contact with the first releasable chip carrier. 
     
     
       10. The method of  claim 1 , wherein the applying a dielectric layer over a surface of the circuit layer comprises sequentially applying multiple dielectric layers over the surface of the circuit layer. 
     
     
       11. The method of  claim 1 , wherein the first activating source is a heat source, and wherein the method includes raising the temperature of an adhesive located between the first releasable chip carrier and the conductive layer to a temperature between 150° C. and 300° C. 
     
     
       12. The method of  claim 1 , wherein the conductive layer includes a thin foil layer and a carrier foil layer, and wherein the releasing the first releasable chip carrier from the conductive layer releases the first releasable chip carrier from the carrier foil layer. 
     
     
       13. The method of  claim 1 , further comprising:
 forming an adhesive layer between the first releasable chip carrier and the conductive layer; and 
 activating the adhesive layer with the first activating source to facilitate the releasing. 
 
     
     
       14. The method of  claim 13 , wherein the adhesive layer is a double sided tape, and wherein the method further comprises an application process selected from the group consisting of applying a thermal release adhesive on one or both sides of the double sided tape and applying a UV release adhesive on one or both sides of the double sided tape. 
     
     
       15. A method for forming semiconductor packages comprising:
 providing a first releasable chip carrier attached to a conductive layer; 
 forming a circuit layer on a surface of the conductive layer; 
 applying a dielectric layer over a surface of the circuit layer; 
 attaching a second releasable chip carrier to a surface of the dielectric layer; 
 releasing, by a first activating source, the first releasable chip carrier from the conductive layer; and 
 operationally testing first circuitry and second circuitry of the circuit layer. 
 
     
     
       16. The method of  claim 15 , wherein results of said operationally testing indicate that the first circuitry and the second circuitry are each operationally functional, and wherein said method further comprises:
 attaching a first semiconductor die to portions of the first circuitry of the circuit layer; 
 attaching a second semiconductor die to portions of the second circuitry of the circuit layer; 
 forming an encapsulating layer surrounding the first semiconductor die and the second semiconductor die; 
 attaching a third releasable chip carrier to a surface of the encapsulating layer; 
 releasing, by a second activating source, the second releasable chip carrier from the surface of the dielectric layer; 
 removing portions of said dielectric layer thereby forming openings within the dielectric layer; 
 forming a first group of ball grid array structures and a second group of ball array structures within the openings, wherein the first group of ball grid array structures are electrically connected to the first semiconductor die, wherein the second group of ball grid array structures are electrically connected to the second semiconductor die; and 
 applying a laser cut between the first semiconductor die and the second semiconductor die and through the conductive layer, the circuit layer, the dielectric layer, and the encapsulating layer thereby forming a first semiconductor structure and a second semiconductor structure as independent singulated semiconductor structures. 
 
     
     
       17. A releasable carrier structure comprising:
 a first releasable chip carrier; 
 a carrier conductive layer; 
 a first releasable tape layer placed between the first releasable chip carrier and the carrier conductive layer, wherein the first releasable tape layer attaches the first releasable chip carrier to the carrier conductive layer, and wherein the first releasable tape layer is configured to release the first releasable chip carrier from the carrier conductive layer after being exposed to an activating source; 
 a dielectric layer formed over a surface of a circuit layer formed over the carrier conductive layer; 
 a second releasable chip carrier; and 
 a second releasable tape layer placed between the second releasable chip carrier and the dielectric layer, wherein the second releasable tape layer attaches the second releasable chip carrier to the dielectric layer, and wherein the second releasable tape layer is configured to release the second releasable chip carrier from the dielectric layer after being exposed to the activating source. 
 
     
     
       18. The releasable carrier structure of  claim 17 , wherein the first releasable chip carrier and the second releasable chip carrier each comprise a size format selected from the group consisting of a panel size format and a strip size format. 
     
     
       19. The releasable carrier structure of  claim 17 , wherein the first releasable chip carrier and the second releasable chip carrier each comprise a panel size format. 
     
     
       20. The releasable carrier structure of  claim 17 , wherein the first releasable chip carrier comprises a panel size format, and wherein the second releasable chip carrier comprises a strip size format.