Chip package structure

Abstract

A chip package structure includes a substrate, a die, a plurality of warpage retainers, and an encapsulant. The substrate has a surface, on which the die is provided. The warpage retainers are provided at at least one corner of the substrate. The encapsulant covers the surface of the substrate, the die and the warpage retainers.

What is claimed is: 
     
       1. A chip package structure, comprising:
 a substrate, having a surface; 
 a die, provided on the surface of the substrate; 
 a plurality of warpage retainers, provided at at least one corner of the surface of the substrate, wherein the plurality of warpage retainers are electrically insulated from the substrate and/or the die; and 
 an encapsulant, covering the surface of the substrate, the die and the plurality of warpage retainers. 
 
     
     
       2. The chip package structure according to  claim 1 , wherein the plurality of warpage retainers comprise four warpage retainers respectively provided at four corners of the surface. 
     
     
       3. The chip package structure according to  claim 2 , wherein the four warpage retainers are triangular. 
     
     
       4. The chip package structure according to  claim 3 , wherein an apex of each of the four warpage retainers faces the respective corner. 
     
     
       5. The chip package structure according to  claim 1 , wherein at least two of the plurality of warpage retainers are provided at one corner of the surface. 
     
     
       6. The chip package structure according to  claim 5 , wherein the corner of the surface is provided with three warpage retainers. 
     
     
       7. The chip package structure according to  claim 6 , wherein the three warpage retainers are in an arrangement having a recess to accommodate corners of the die or a bonding wire. 
     
     
       8. The chip package structure according to  claim 7 , wherein the three warpage retainers are rectangular. 
     
     
       9. The chip package structure according to  claim 1 , wherein the plurality of warpage retainers comprise only two warpage retainers respectively provided at two adjacent corners of the surface. 
     
     
       10. The chip package structure according to  claim 1 , wherein a ratio of an area of each of the plurality of warpage retainers to an area of the surface is greater than 1%. 
     
     
       11. The chip package structure according to  claim 1 , wherein a ratio of a total area of the plurality of warpage retainers to an area of the surface is greater than 4%. 
     
     
       12. The chip package structure according to  claim 1 , wherein each of the plurality of warpage retainers is a passive device.