Method of optimizing wire RC for device performance and reliability

Abstract

A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.

What is claimed is: 
     
       1. A computer program product for tailoring BEOL RC parametrics to improve chip performance in an integrated circuit design, said computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being readable and executable by a computerized device to cause said computerized device to perform a method comprising:
 analyzing a circuit design for an integrated circuit chip, said analyzing comprising determining Vmax for vias and metal lines in said circuit design over a range of sizes for said vias and metal lines, Vmax defining spacing between features on the integrated circuit chip due to time dependent dielectric breakdown based on-device characteristics; 
 determining predicted use voltage for applications on said integrated circuit chip; 
 comparing said predicted use voltage to said Vmax determined for said vias and metal lines; and 
 creating a modified circuit design based on performance parameters of said integrated circuit chip, said modified circuit design using a lower voltage for Vmax. 
 
     
     
       2. The computer program product according to  claim 1 , said method further comprising:
 tailoring the size or the location of at least one of said vias and said metal lines based on performance parameters of said integrated circuit chip. 
 
     
     
       3. The computer program product according to  claim 1 , said method further comprising:
 providing printing and etching instructions for said vias and said metal lines according to said modified circuit design. 
 
     
     
       4. The computer program product according to  claim 1 , said determining said predicted use voltage comprising using test and inline data to predict the use voltage that said integrated circuit chip will actually experience in applications. 
     
     
       5. The computer program product according to  claim 4 , said determining said predicted use voltage being done on lot, wafer, or chip basis. 
     
     
       6. The computer program product according to  claim 1 , said method further comprising:
 verifying said predicted use voltage being consistent with said lower voltage for Vmax. 
 
     
     
       7. The computer program product according to  claim 6 , said verifying further comprising determining frequency measurements of at least one performance sensitive ring oscillator (PSRO). 
     
     
       8. A system, comprising:
 a data processor; and 
 a memory connected to said data processor, wherein
 said data processor obtains a first file from said memory, wherein said first file contains a circuit design for an integrated circuit chip, 
 said data processor analyzes said circuit design for said integrated circuit chip by determining Vmax for vias and metal lines in said circuit design over a range of sizes for said vias and said metal lines, said Vmax defining spacing between features on the integrated circuit chip due to time dependent dielectric breakdown based on device characteristics, 
 said data processor determines predicted use voltage for applications on said integrated circuit chip, 
 said data processor compares said predicted use voltage to said Vmax determined for said vias and metal lines, 
 said data processor creates a modified circuit design based on performance parameters of said integrated circuit chip, said modified circuit design using a lower voltage for Vmax, and 
 said data processor stores said modified circuit design in a second file in said memory. 
 
 
     
     
       9. The system according to  claim 8 , wherein creating a modified circuit design based on performance parameters of said integrated circuit chip further comprises said data processor tailoring one of the size and the location of at least one of said vias and said metal lines based on performance parameters of said integrated circuit chip. 
     
     
       10. The system according to  claim 8 , wherein determining said predicted use voltage comprises using test and inline data to predict the use voltage that said integrated circuit chip will actually experience in applications. 
     
     
       11. The system according to  claim 10 , said determining said predicted use voltage being done on lot, wafer, or chip basis. 
     
     
       12. The system according to  claim 8 , further comprising:
 said data processor verifying said predicted use voltage being consistent with said lower voltage for Vmax. 
 
     
     
       13. The system according to  claim 12 , further comprising:
 at least one performance sensitive ring oscillator (PSRO), wherein said verifying further comprises determining frequency measurements of said at least one PSRO. 
 
     
     
       14. The system according to  claim 8 , further comprising:
 manufacturing equipment, wherein said vias and said metal lines are printed and etched according to said modified circuit design. 
 
     
     
       15. A computer program product for tailoring BEOL RC parametrics in an integrated circuit design, said computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being readable and executable by a computerized device to cause said computerized device to perform a method comprising:
 determining maximum voltages defining a range of sizes for spaces between vias and metal lines in an integrated circuit design due to time dependent dielectric breakdown based on device characteristics; 
 determining predicted use voltage for applications on an integrated circuit chip having said integrated circuit design; and 
 using said predicted use voltage to adjust one of the size and the location of at least one of said vias and said metal lines in said integrated circuit design according to said range of sizes for said spaces between said vias and said metal lines while keeping said predicted use voltage below the maximum voltage associated with a selected space. 
 
     
     
       16. The computer program product according to  claim 15 , said method further comprising:
 creating a modified circuit design based on performance parameters of said integrated circuit chip, said modified circuit design using a predicted use voltage below the maximum voltage associated with said selected space. 
 
     
     
       17. The computer program product according to  claim 16 , said modified circuit design being based on performance parameters of said integrated circuit chip using selected sizes of said vias and said metal lines. 
     
     
       18. The computer program product according to  claim 16 , said method further comprising:
 providing printing and etching instructions for said vias and said metal lines according to said modified circuit design. 
 
     
     
       19. The computer program product according to  claim 15 , said determining said predicted use voltage comprising using test and inline data to predict the use voltage that said integrated circuit chip will actually experience in applications. 
     
     
       20. The computer program product according to  claim 15 , said method further comprising:
 verifying said predicted use voltage being consistent with a lower voltage for the maximum voltage associated with said selected space.