Vertical field-effect transistor (VFET) devices and methods of forming the same

Abstract

Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

What is claimed is: 
     
       1. A method of forming a vertical field-effect transistor (VFET) device, the method comprising:
 forming a channel region that protrudes from an upper surface of a substrate and extends longitudinally in a first horizontal direction, wherein the channel region comprises a first channel region and a second channel region, which are aligned in the first horizontal direction, and the first channel region and the second channel region overlap a first portion and a second portion of the substrate, respectively; 
 forming a first cavity in the substrate by removing the first portion of the substrate, wherein the first cavity exposes a lower surface of the first channel region; 
 forming a first bottom source/drain in the first cavity of the substrate; 
 forming a second cavity in the substrate by removing the second portion of the substrate, wherein the second cavity exposes a lower surface of the second channel region; 
 forming a second bottom source/drain in the second cavity of the substrate; 
 after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region; and 
 forming a first gate structure on a side of the first channel region and forming a second gate structure on a side of the second channel region. 
 
     
     
       2. The method of  claim 1 , wherein the first bottom source/drain comprises a first protruding portion protruding from an upper surface of the first bottom source/drain toward the first channel region,
 wherein the second bottom source/drain comprises a second protruding portion protruding from an upper surface of the second bottom source/drain toward the second channel region, and 
 wherein the first protruding portion has a first thickness in a vertical direction, the second protruding portion has a second thickness in the vertical direction, and the first thickness and the second thickness are different. 
 
     
     
       3. The method of  claim 1 , wherein the first bottom source/drain comprises a material different from the second bottom source/drain. 
     
     
       4. The method of  claim 3 , wherein forming the first bottom source/drain is performed before forming the second bottom source/drain, and
 wherein the first bottom source/drain comprises a bottom source/drain of an N-type field-effect transistor, and the second bottom source/drain comprises a bottom source/drain of a P-type field-effect transistor. 
 
     
     
       5. The method of  claim 1 , further comprising forming a protecting layer extending on a side of the channel region, wherein forming the first cavity and forming the second cavity are performed while the protecting layer is on the side of the channel region. 
     
     
       6. The method of  claim 1 , wherein forming the first cavity comprises removing a lower portion of the first channel region, and forming the second cavity comprises removing a lower portion of the second channel region. 
     
     
       7. The method of  claim 1 , wherein forming the second cavity is performed after forming the first bottom source/drain. 
     
     
       8. The method of  claim 1 , wherein the first cavity exposes an entirety of the lower surface of the first channel region, and
 wherein the second cavity exposes an entirety of the lower surface of the second channel region. 
 
     
     
       9. The method of  claim 1 , wherein forming the channel region comprises:
 forming a mask layer on the substrate; and 
 etching the substrate using the mask layer as an etch mask to form the channel region. 
 
     
     
       10. The method of  claim 1 , wherein forming the channel region comprises forming a plurality of channel regions on the substrate,
 wherein each of the plurality of channel regions extends longitudinally in the first horizontal direction, and the plurality of channel regions are spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction, 
 wherein each of the plurality of channel regions comprises a respective one of a plurality of first channel regions and a respective one of a plurality of second channel regions, 
 wherein the plurality of first channel regions overlap the first bottom source/drain, 
 wherein the plurality of second channel regions overlap the second bottom source/drain, and 
 wherein removing the portion of the channel region between the first channel region and the second channel region comprises removing a plurality of portions, respectively, of the plurality of channel regions to separate the plurality of first channel regions from the plurality of second channel regions. 
 
     
     
       11. A method of forming a vertical field-effect transistor (VFET) device, the method comprising:
 forming a channel region on a substrate, wherein the channel region extends longitudinally in a first horizontal direction and comprises a first channel region and a second channel region, which are aligned in the first horizontal direction; 
 forming a first bottom source/drain in the substrate, the first channel region overlapping the first bottom source/drain; 
 forming a second bottom source/drain in the substrate, the second channel region overlapping the second bottom source/drain; 
 after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region; and 
 forming a first gate structure on a side of the first channel region and a second gate structure on a side of the second channel region, 
 wherein the first bottom source/drain comprises a first protruding portion protruding from an upper surface of the first bottom source/drain toward the first channel region, and 
 wherein the second bottom source/drain comprises a second protruding portion protruding from an upper surface of the second bottom source/drain toward the second channel region. 
 
     
     
       12. The method of  claim 11 , wherein the first channel region comprises a lower surface facing the first bottom source/drain, and wherein an entirety of the lower surface of the first channel region contacts the first bottom source/drain, and
 wherein the second channel region comprises a lower surface facing the second bottom source/drain, and wherein an entirety of the lower surface of the second channel region contacts the second bottom source/drain. 
 
     
     
       13. The method of  claim 11 ,
 wherein the first protruding portion has a first thickness in a vertical direction, the second protruding portion has a second thickness in the vertical direction, and the first thickness is different from the second thickness. 
 
     
     
       14. The method of  claim 11 , wherein forming the channel region comprises:
 forming a mask layer on the substrate; and 
 etching the substrate using the mask layer as an etch mask to form the channel region. 
 
     
     
       15. The method of  claim 11 , wherein forming the first bottom source/drain is performed before forming the second bottom source/drain, and
 wherein the first bottom source/drain is a bottom source/drain of an N-type field-effect transistor, and the second bottom source/drain is a bottom source/drain of a P-type field-effect transistor. 
 
     
     
       16. The method of  claim 11 , wherein the first channel region comprises a plurality of first channel regions that are spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction, and each of the plurality of first channel regions overlaps the first bottom source/drain, and
 wherein the second channel region comprises a plurality of second channel regions that are spaced apart from each other in the second horizontal direction, and each of the plurality of second channel regions overlaps the second bottom source/drain. 
 
     
     
       17. The method of  claim 11 , wherein the first protruding portion of the first bottom source/drain contacts the first channel region, and each of the first channel region and the first protruding portion of the first bottom source/drain has a first width in a second horizontal direction that is perpendicular to the first horizontal direction at an interface between the first channel region and the first protruding portion of the first bottom source/drain. 
     
     
       18. A method of forming a vertical field-effect transistor (VFET) device, the method comprising:
 forming a channel region on a substrate, wherein the channel region extends longitudinally in a first horizontal direction and comprises a first channel region and a second channel region, which are arranged in the first horizontal direction; 
 forming a first cavity in the substrate; 
 forming a first bottom source/drain in the first cavity, the first channel region contacting the first bottom source/drain; 
 after forming the first bottom source/drain, forming a second cavity in the substrate; 
 forming a second bottom source/drain in the second cavity, the second channel region contacting the second bottom source/drain; 
 after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region; and 
 forming a first gate structure on a side of the first channel region and a second gate structure on a side of the second channel region. 
 
     
     
       19. The method of  claim 18 , wherein the second cavity exposes a portion of the first bottom source/drain, and the second bottom source/drain contacts the first bottom source/drain. 
     
     
       20. The method of  claim 18 , wherein the first channel region comprises a lower portion connected to the substrate, and forming the first cavity comprises removing the lower portion of the first channel region.