Scalable connectivity verification using conditional cut-points

Abstract

Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

What is claimed is: 
     
       1. A method for performing connectivity verification of an integrated circuit device, the method comprising:
 determining target gates within the integrated circuit device; 
 finding trace signals within the integrated circuit device; 
 determining nested trace signals of the trace signals; 
 determining one or more locations on the integrated circuit device for cut points for non-nested trace signals of the trace signals; and 
 performing connectivity verification using the one or more locations for the cut points. 
 
     
     
       2. The method of  claim 1 , further comprising:
 creating a conditional cut point for each nested trace signal of the trace signals. 
 
     
     
       3. The method of  claim 2 , further comprising:
 placing a multiplexer at one or more of the conditional cut points; and 
 performing connectivity verification at the conditional cut point of said each nested trace signal. 
 
     
     
       4. The method of  claim 3 , wherein:
 the multiplexer is configured with two inputs such that a nondeterministic constant is at a first input and a signal input into the multiplexer is a second input. 
 
     
     
       5. The method of  claim 1 , further comprising:
 creating a directed graph representation of the integrated circuit device by defining blocks of the integrated circuit device; and 
 determining interconnections of the blocks. 
 
     
     
       6. The method of  claim 5 , wherein:
 the blocks are chosen from registers, AND gates, OR gates, NOR gates, NAND gates, XOR gates, constants, and primary input gates. 
 
     
     
       7. The method of  claim 5 , wherein:
 the determining nested trace signals comprises performing an iterative depth first search fan-out traversal of trace signals from the directed graph representation. 
 
     
     
       8. The method of  claim 7 , further comprising:
 creating a graph wherein nodes of the graph are trace signals and edges of the graph are connections from one trace signal to another trace signal of the trace signals. 
 
     
     
       9. The method of  claim 1 , wherein:
 the connectivity verification is configured to verify proper propagation of signals between blocks within the integrated circuit device. 
 
     
     
       10. The method of  claim 1 , wherein:
 the performing connectivity verification comprises FAIL verification configured to check for correct propagation of a trace signal to a trace array. 
 
     
     
       11. The method of  claim 1 , wherein:
 the performing connectivity verification comprises COVER verification configured to check for the ability of initialization logic to sensitize a mode condition. 
 
     
     
       12. A method for performing connectivity verification of an integrated circuit device, the method comprising:
 receiving a mode condition for each entry in a hardware specification of the integrated circuit device; 
 determining whether a lower module is referred to for each entry of a plurality of entries; 
 based on determining that a lower module specification is present at an entry of the plurality of entries, creating a conditional cut point at said entry; and 
 performing connectivity verification using one or more locations on the integrated circuit device for cut points for non-nested trace signals. 
 
     
     
       13. The method of  claim 12 , further comprising:
 placing a multiplexer at one or more of the conditional cut points; and 
 performing connectivity verification at each conditional cut point of the one or more conditional cut points. 
 
     
     
       14. The method of  claim 13 , wherein:
 the multiplexer is configured with two inputs such that a nondeterministic constant is at a first input and a signal input into the multiplexer is a second input. 
 
     
     
       15. The method of  claim 12 , further comprising:
 creating a directed graph representation of integrated circuit device; and 
 determining nest trace signals. 
 
     
     
       16. The method of  claim 15 , wherein:
 the creating the directed graph representation comprises defining blocks of the integrated circuit device; and 
 determining interconnections of the blocks. 
 
     
     
       17. The method of  claim 16 , wherein:
 the blocks are chosen from registers, AND gates, OR gates, NOR gates, NAND gates, XOR gates, constants, and primary input gates. 
 
     
     
       18. The method of  claim 15 , wherein:
 the determining nested trace signals comprises performing an iterative depth first search fan-out traversal of trace signals from the directed graph representation. 
 
     
     
       19. The method of  claim 18 , further comprising:
 creating a graph wherein nodes of the graph are trace signals and edges of the graph are connections from one trace signal to another trace signal of the trace signals. 
 
     
     
       20. A computer program product for performing connectivity verification of an integrated circuit device, the computer program product comprising:
 a computer-readable storage medium having program instructions embodied therewith, wherein the computer-readable storage medium is not a transitory signal per se, the program instructions readable by a processor system to cause the processor system to perform a method comprising:
 receiving a hardware definition of the integrated circuit device; 
 determining target gates within the integrated circuit device; 
 finding trace signals within the integrated circuit device; 
 determining nested trace signals of the trace signals; 
 determining one or more locations on the integrated circuit device for cut points for non-nested trace signals of the trace signals; and 
 performing connectivity verification using the one or more locations for the cut points.