US10978549B2ActiveUtilityA1
Semiconductor device and method for fabricating the same
Est. expirySep 5, 2039(~13.2 yrs left)· nominal 20-yr term from priority
Inventors:Tse-Yao Huang
H10P 14/6922H10P 14/6529H10P 14/6526H10P 14/6506H10P 14/6334H10W 20/43H10W 20/435H10D 1/716H10D 1/68C23C 16/401H01L 21/02332H01L 21/02126H01L 23/528H01L 28/40H01L 21/02304H01L 21/02271H01L 21/02337H10B 12/033H10B 12/485H10B 12/02H10B 12/0335H10B 12/482H10B 12/315
82
PatentIndex Score
2
Cited by
8
References
18
Claims
Abstract
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a conductive feature comprising tungsten positioned above the substrate, a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature, and a plurality of capacitor structures positioned above the substrate.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A semiconductor device, comprising:
a substrate;
a conductive feature comprising tungsten positioned above the substrate;
a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature;
a plurality of capacitor structures positioned above the substrate; and
a plurality of word lines positioned in the substrate and a doped region positioned between an adjacent pair of the plurality of word lines, wherein the conductive feature is positioned on the doped region.
2. The semiconductor device of claim 1 , wherein the conductive feature is positioned below the plurality of capacitor structures.
3. The semiconductor device of claim 1 , wherein the conductive feature is positioned above the plurality of capacitor structures.
4. The semiconductor device of claim 1 , further comprising a plurality of isolation structures positioned in the substrate, wherein the plurality of isolation structures are separated from each other and define a plurality of active regions of the substrate.
5. The semiconductor device of claim 4 , further comprising a doped region, wherein each of the plurality of active regions intersects two word lines, the doped region is positioned between one of the two word lines and one of the plurality of isolation structures, and the conductive feature is positioned on the doped region.
6. The semiconductor device of claim 5 , wherein the two word lines extend along a first direction and the plurality of active regions extend along a direction that is slanted with respect to the first direction.
7. The semiconductor device of claim 1 , further comprising a plurality of bit line contacts positioned above the substrate and a plurality of bit lines positioned above the substrate, wherein one of the plurality of bit line contacts is positioned on the coverage layer and is positioned under one of the plurality of bit lines.
8. The semiconductor device of claim 7 , wherein the plurality of bit lines are formed as wavy lines.
9. The semiconductor device of claim 1 , further comprising a plurality of bit lines positioned above the substrate, wherein the plurality of word lines extend along a first direction, the plurality of bit lines extend along a second direction, and the first direction is perpendicular to the second direction.
10. The semiconductor device of claim 1 , wherein the plurality of capacitor structures comprise a plurality of bottom electrodes inwardly positioned above the substrate, a capacitor insulating layer positioned on the plurality of bottom electrodes, and a top electrode positioned on the capacitor insulating layer.
11. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a conductive feature comprising tungsten positioned above the substrate; and
forming a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature; and
cleaning the conductive feature before forming a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature, wherein cleaning the conductive feature comprises applying a reducing agent to the top surface of the conductive feature, and the reducing agent is titanium tetrachloride, tantalum tetrachloride, or a combination thereof.
12. The method for fabricating the semiconductor device of claim 11 , further comprising forming a plurality of capacitor structures positioned above the substrate.
13. The method for fabricating the semiconductor device of claim 12 , wherein the conductive feature is positioned below the plurality of capacitor structures.
14. The method for fabricating the semiconductor device of claim 12 , wherein the conductive feature is positioned above the plurality of capacitor structures.
15. The method for fabricating the semiconductor device of claim 12 , further comprising forming a plurality of word lines positioned in the substrate and a doped region positioned between an adjacent pair of the plurality of word lines, wherein the conductive feature is positioned on the doped region.
16. The method for fabricating the semiconductor device of claim 12 , further comprising forming a plurality of bit line contacts and a plurality of bit lines, wherein one of the plurality of bit line contacts is positioned on the coverage layer and is positioned under one of the plurality of bit lines.
17. The method for fabricating the semiconductor device of claim 16 , wherein the plurality of bit lines are formed as wavy lines.
18. The method for fabricating the semiconductor device of claim 16 , wherein the plurality of capacitor structures comprise a plurality of bottom electrodes inwardly positioned above the substrate, a capacitor insulating layer positioned on the plurality of bottom electrodes, and a top electrode positioned on the capacitor insulating layer.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.