Magnetic shielding structure for MRAM array

Abstract

Embodiments are provided for a packaged semiconductor device including: a semiconductor die having an active side and an opposite back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM area on the active side of the semiconductor die; and a top cover including a soft-magnetic material positioned on the back side of the semiconductor die, wherein the top cover includes a recess formed in a first major surface of the top cover, the first major surface faces the back side of the semiconductor die, and the recess is positioned over the MRAM cell array.

What is claimed is: 
     
       1. A packaged semiconductor device comprising:
 a semiconductor die having an active side and an opposite back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM area on the active side of the semiconductor die, the semiconductor die also having active circuitry formed within a circuitry area on the active side, the active circuitry laterally adjacent to the MRAM cell array; and 
 a top cover comprising a soft-magnetic material positioned on the back side of the semiconductor die, wherein
 the top cover comprises a recess formed in a first major surface of the top cover, 
 the first major surface faces the back side of the semiconductor die, and 
 the recess is positioned over the MRAM cell array, wherein:
 a first portion of the semiconductor die has a first thickness in the circuitry area, 
 a second portion of the semiconductor die has a second thickness in the MRAM area that is greater than the first thickness, the second portion forming a stack positioned vertically adjacent to the MRAM cell array, and 
 the recess is sized to fit over and surround the stack. 
 
 
 
     
     
       2. The packaged semiconductor device of  claim 1 , wherein
 sidewalls of the recess are separated from a perimeter of the MRAM cell array by a spacing distance. 
 
     
     
       3. The packaged semiconductor device of  claim 1 , wherein
 the recess is formed to a depth that corresponds to a difference between a back side of the semiconductor die in the circuitry area and a back side of the semiconductor die in the MRAM area. 
 
     
     
       4. The packaged semiconductor device of  claim 1 , wherein
 the first major surface of the top cover makes direct contact with the back side of the semiconductor die in the circuitry area. 
 
     
     
       5. The packaged semiconductor device of  claim 1 , further comprising:
 a mold body directly contacts and attaches to lateral edges of the top cover and to the back side of the semiconductor die in the circuitry area. 
 
     
     
       6. The packaged semiconductor device of  claim 1 , wherein
 the first major surface of the top cover is attached with adhesive to the back side of the semiconductor die in the circuitry area. 
 
     
     
       7. The packaged semiconductor device of  claim 1 , wherein
 an inner surface of the recess is attached with adhesive to sidewalls and back side of the stack. 
 
     
     
       8. A packaged semiconductor device comprising:
 a semiconductor die having an active side and an opposite back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM area on the active side of the semiconductor die; 
 a top cover comprising a soft-magnetic material positioned on the back side of the semiconductor die, wherein
 the top cover comprises a recess formed in a first major surface of the top cover, 
 the first major surface faces the back side of the semiconductor die, and 
 the recess is positioned over the MRAM cell array; 
 
 a redistributed layer (RDL) structure formed over the active side of the semiconductor die wherein lateral edges of the semiconductor die extend fully to lateral edges of the RDL structure such that the lateral edges of the RDL structure are coincident to the lateral edges of the die, the RDL structure comprising a plurality of metal structures that electrically contact a plurality of die pads on the active side of the semiconductor die, the plurality of metal structures providing a plurality of external contact pads on an outermost surface of the RDL structure; 
 a plurality of solder balls attached to the plurality of external contact pads; and 
 a bottom cover comprising the soft-magnetic material having a second major surface positioned on the outermost surface of the RDL structure wherein
 the bottom cover comprises a plurality of openings aligned to the plurality of solder balls wherein each opening of the plurality of openings surrounds at least a portion of a solder ball of the plurality of solder balls. 
 
 
     
     
       9. The packaged semiconductor device of  claim 8 , wherein
 a combined height is measured between the second major surface of the bottom cover and the first major surface of the top cover, and 
 a lateral spacing distance between sidewalls of the recess and a perimeter of the MRAM cell array has a larger value than the combined height. 
 
     
     
       10. The packaged semiconductor device of  claim 8 , wherein
 lateral edges of the bottom cover overlap at least a portion of the lateral width of sidewall portions of the top cover. 
 
     
     
       11. The packaged semiconductor device of  claim 8 , wherein
 the semiconductor die is one of a plurality of semiconductor dies in a panel, 
 the top cover is one of a plurality of top covers positioned on back sides of the plurality of semiconductor dies, 
 the RDL structure is one of a plurality of RDL structures formed over active sides of the plurality of semiconductor dies, 
 the plurality of solder balls are part of a larger plurality of solder balls attached to the plurality of external contact pads on outermost surfaces of each of the plurality of RDL structures, and 
 the bottom cover is one of a plurality of bottom covers positioned on outermost surfaces of the plurality of RDL structures. 
 
     
     
       12. A packaged semiconductor device, comprising:
 a semiconductor die having an active side and an opposite back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM area on the active side of the semiconductor die; 
 a top cover comprising a soft-magnetic material positioned on the back side of the semiconductor die, wherein
 the top cover comprises a recess formed in a first major surface of the top cover, 
 the first major surface faces the back side of the semiconductor die, and 
 the recess is positioned over the MRAM cell array, and 
 the soft-magnetic material is a material that is configured to be magnetized in a magnetic field and not magnetized when the magnetic field is removed; and 
 
 a bottom cover comprising the soft-magnetic material positioned on the active side of the semiconductor die, wherein
 the bottom cover comprises a plurality of openings aligned to a plurality of die pads on the active side of the semiconductor die; and 
 a plurality of solder balls attached to the plurality of die pads, wherein each opening of the plurality of openings surrounds at least a portion of a solder ball of the plurality of solder balls. 
 
 
     
     
       13. The packaged semiconductor device of  claim 8 , further comprising:
 a printed circuit board (PCB) having a plurality of bond pads on a front side of the PCB, wherein:
 the plurality of solder balls are attached to the plurality of bond pads through the plurality of openings in the bottom cover. 
 
 
     
     
       14. The packaged semiconductor device of  claim 1 , further comprising:
 a second top cover comprising the soft-magnetic material, a second recess formed in a first major surface of the second top cover, wherein
 the semiconductor die further comprises a second MRAM array, and 
 the second recess is positioned over the second MRAM cell array. 
 
 
     
     
       15. The packaged semiconductor device of  claim 1 , wherein
 the semiconductor die further comprises a second MRAM array, and 
 the top cover further comprises a second recess formed in the first major surface of the top cover, the second recess positioned over the second MRAM cell array. 
 
     
     
       16. The packaged semiconductor device of  claim 1 , wherein
 the soft-magnetic material has a relative permeability greater than 50. 
 
     
     
       17. The packaged semiconductor device of  claim 8 , wherein the soft-magnetic material is a material that is configured to be magnetized in a magnetic field and not magnetized when the magnetic field is removed. 
     
     
       18. The packaged semiconductor device of  claim 8 , wherein the RDL structure is formed directly on the active side of the semiconductor die. 
     
     
       19. The packaged semiconductor device of  claim 8 , wherein
 a second portion of the semiconductor die has the first thickness in the MRAM area, and 
 an inner surface of the recess is attached with adhesive to the back side of the semiconductor die in the MRAM area.