US11024704B1ActiveUtility
Manufacturing method of capacitor structure
Assignee: UNITED SEMICONDUCTOR XIAMEN CO LTDPriority: Feb 5, 2020Filed: Feb 26, 2020Granted: Jun 1, 2021
Est. expiryFeb 5, 2040(~13.6 yrs left)· nominal 20-yr term from priority
H10D 1/711H10D 1/694H10D 1/684H10D 1/68H01L 28/65H01L 28/56H01L 28/82
84
PatentIndex Score
2
Cited by
3
References
20
Claims
Abstract
A manufacturing method of a capacitor structure includes the following steps. A first capacitor is formed on a substrate. The first capacitor includes a first electrically conductive pattern and a second electrically conductive pattern of a first electrically conductive layer and a first dielectric layer disposed therebetween in a horizontal direction. A second capacitor is formed on the substrate before forming the first capacitor. The second capacitor includes a third electrically conductive pattern and a fourth electrically conductive pattern of a second electrically conductive layer and a second dielectric layer disposed therebetween in the horizontal direction. A thickness of the second electrically conductive layer is monitored. A target value of a thickness of the first electrically conductive layer is controlled in accordance with a value of a monitored thickness of the second electrically conductive layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A manufacturing method of a capacitor structure, comprising:
forming a first capacitor on a substrate, wherein the first capacitor comprises:
a first electrically conductive pattern of a first electrically conductive layer;
a second electrically conductive pattern of the first electrically conductive layer; and
a first dielectric layer disposed between the first electrically conductive pattern and the second electrically conductive pattern in a horizontal direction;
forming a second capacitor on the substrate before the step of forming the first capacitor, wherein the second capacitor comprises:
a third electrically conductive pattern of a second electrically conductive layer;
a fourth electrically conductive pattern of the second electrically conductive layer; and
a second dielectric layer disposed between the third electrically conductive pattern and the fourth electrically conductive pattern in the horizontal direction;
monitoring a thickness of the second electrically conductive layer; and
controlling a target value of a thickness of the first electrically conductive layer in accordance with a value of a monitored thickness of the second electrically conductive layer.
2. The manufacturing method of the capacitor structure according to claim 1 , wherein the first capacitor and the second capacitor comprise a metal-oxide-metal (MOM) capacitor respectively.
3. The manufacturing method of the capacitor structure according to claim 1 , wherein the controlling the target value of the thickness of the first electrically conductive layer comprises:
adjusting the target value of the thickness of the first electrically conductive layer when the value of the monitored thickness of the second electrically conductive layer is out of a predetermined range; and
keeping the target value of the thickness of the first electrically conductive layer unchanged when the value of the monitored thickness of the second electrically conductive layer is within the predetermined range.
4. The manufacturing method of the capacitor structure according to claim 3 , wherein the first capacitor is the nth capacitor unit of a plurality of capacitor units stacked on the substrate, the first electrically conductive layer is the nth metal layer of a plurality of metal layers stacked on the substrate, and a target value of a thickness of the nth metal layer is calculated by a following equation:
T
3
n
=
R
S
n
-
∑
k
=
1
n
-
1
X
k
×
T
2
k
×
C
2
k
X
n
×
C
2
n
wherein T 3n stands for the target value of the thickness of the nth metal layer,
X k stands for a coefficient of sheet resistance of the kth metal layer of the plurality of the metal layers versus capacitance of the kth capacitor unit of the plurality of the capacitor units,
X n stands for a coefficient of sheet resistance of the nth metal layer versus capacitance of the nth capacitor unit,
T 2k stands for a value of a monitored thickness of the kth metal layer,
C 2k stands for a value of a monitored critical dimension of the kth metal layer,
C 2n stands for a value of a monitored critical dimension of the nth metal layer,
RS n stands for a design value of sheet resistance of the metal layers from the first metal layer to the nth metal layer of the plurality of the metal layers,
k is a positive integer, and
n is a positive integer larger than 1.
5. The manufacturing method of the capacitor structure according to claim 4 , wherein the design value of the sheet resistance of the metal layers from the first metal layer to the nth metal layer of the plurality of the metal layers is calculated by a following equation:
R
S
n
=
∑
k
=
1
n
X
k
×
T
1
k
×
C
1
k
wherein T 1k stands for a design value of a thickness of the kth metal layer, and C 1k stands for a design value of a critical dimension of the kth metal layer.
6. The manufacturing method of the capacitor structure according to claim 4 , wherein each of the plurality of the capacitor units comprises a metal-oxide-metal (MOM) capacitor unit.
7. The manufacturing method of the capacitor structure according to claim 4 , wherein the plurality of the capacitor units are electrically connected with one another.
8. The manufacturing method of the capacitor structure according to claim 4 , wherein the plurality of the capacitor units are electrically connected with one another in parallel.
9. The manufacturing method of the capacitor structure according to claim 3 , wherein the target value of the thickness of the first electrically conductive layer is calculated by a following equation:
T
3
A
=
R
S
A
-
X
B
×
T
2
B
×
C
2
B
X
A
×
C
2
A
wherein T 3A stands for the target value of the thickness of the first electrically conductive layer,
X A stands for a coefficient of sheet resistance of the first electrically conductive layer versus capacitance of the first capacitor,
X B stands for a coefficient of sheet resistance of the second electrically conductive layer versus capacitance of the second capacitor,
T 2B stands for the value of the monitored thickness of the second electrically conductive layer,
C 2A stands for a value of a monitored critical dimension of the first electrically conductive layer,
C 2B stands for a value of a monitored critical dimension of the second electrically conductive layer, and
RS A stands for a design value of sheet resistance of the first electrically conductive layer and the second electrically conductive layer.
10. The manufacturing method of the capacitor structure according to claim 9 , wherein the design value of the sheet resistance of the first electrically conductive layer and the second electrically conductive layer is calculated by a following equation:
RS A =X A ×T 1A ×C 1A +X B ×T 1B ×C 1B
wherein T 1A stands for a design value of the thickness of the first electrically conductive layer,
T 1B stands for a design value of the thickness of the second electrically conductive layer,
C 1A stands for a design value of a critical dimension of the first electrically conductive layer, and
C 1B stands for a design value of a critical dimension of the second electrically conductive layer.
11. The manufacturing method of the capacitor structure according to claim 9 , wherein the first capacitor is electrically connected with the second capacitor.
12. The manufacturing method of the capacitor structure according to claim 9 , wherein the first capacitor is electrically connected with the second capacitor in parallel.
13. The manufacturing method of the capacitor structure according to claim 3 , further comprising:
forming a third capacitor on the substrate after the step of forming the first capacitor, wherein the third capacitor comprises:
a fifth electrically conductive pattern of a third electrically conductive layer;
a sixth electrically conductive pattern of the third electrically conductive layer; and
a third dielectric layer disposed between the fifth electrically conductive pattern and the sixth electrically conductive pattern in the horizontal direction; and
adjusting a target value of a thickness of the third electrically conductive layer, wherein the target value of the thickness of the third electrically conductive layer is calculated by a following equation:
T
3
C
=
R
S
C
-
X
B
×
T
2
B
×
C
2
B
-
X
A
×
T
2
A
×
C
2
A
X
C
×
C
2
C
wherein T 3C stands for the target value of the thickness of the third electrically conductive layer,
X A stands for a coefficient of sheet resistance of the first electrically conductive layer versus capacitance of the first capacitor,
X B stands for a coefficient of sheet resistance of the second electrically conductive layer versus capacitance of the second capacitor,
X C stands for a coefficient of sheet resistance of the third electrically conductive layer versus capacitance of the third capacitor,
T 2A stands for a value of a monitored thickness of the first electrically conductive layer,
T 2B stands for the value of the monitored thickness of the second electrically conductive layer,
C 2A stands for a value of a monitored critical dimension of the first electrically conductive layer,
C 2B stands for a value of a monitored critical dimension of the second electrically conductive layer,
C 2C stands for a value of a monitored critical dimension of the third electrically conductive layer, and
RS C stands for a design value of sheet resistance of the first electrically conductive layer, the second electrically conductive layer, and the third electrically conductive layer.
14. The manufacturing method of the capacitor structure according to claim 13 , wherein the design value of the sheet resistance of the first electrically conductive layer, the second electrically conductive layer, and the third electrically conductive layer is calculated by a following equation:
RS C =X A ×T 1A ×C 1A +X B ×T 1B ×C 1B +X C ×T 1C ×C 1C ,
wherein T 1A stands for a design value of the thickness of the first electrically conductive layer,
T 1B stands for a design value of the thickness of the second electrically conductive layer,
T 1C stands for a design value of the thickness of the third electrically conductive layer,
C 1A stands for a design value of a critical dimension of the first electrically conductive layer,
C 1B stands for a design value of a critical dimension of the second electrically conductive layer, and
C 1C stands for a design value of a critical dimension of the third electrically conductive layer.
15. The manufacturing method of the capacitor structure according to claim 13 , wherein the first capacitor, the second capacitor, and the third capacitor are electrically connected with one another.
16. The manufacturing method of the capacitor structure according to claim 15 , wherein the first capacitor, the second capacitor, and the third capacitor are electrically connected with one another in parallel.
17. The manufacturing method of the capacitor structure according to claim 3 , wherein a method of forming the first electrically conductive layer comprises:
forming trenches in the first dielectric layer;
forming an electrically conductive material on the first dielectric layer and in the trenches; and
performing a planarization process to the electrically conductive material for removing the electrically conductive material outside the trenches.
18. The manufacturing method of the capacitor structure according to claim 17 , wherein the planarization process is performed in accordance with an adjusted target value of the thickness of the first electrically conductive layer when the value of the monitored thickness of the second electrically conductive layer is out of the predetermined range.
19. The manufacturing method of the capacitor structure according to claim 17 , wherein the planarization process is performed in accordance with an unchanged target value of the thickness of the first electrically conductive layer when the value of the monitored thickness of the second electrically conductive layer is within the predetermined range.
20. The manufacturing method of the capacitor structure according to claim 1 , wherein the horizontal direction is parallel to a surface of the substrate.Cited by (0)
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