Semiconductor structure having word line disposed over portion of an oxide-free dielectric material in the non-active region

Abstract

A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.

What is claimed is: 
     
       1. A semiconductor structure, comprising:
 a substrate having an active region and a non-active region adjacent to the active region, wherein the active region has a first trench; 
 a buried gate electrode disposed in the first trench; 
 a gate dielectric layer interposed between the buried gate electrode and the first trench; 
 an oxide-free dielectric material disposed over the non-active region of the substrate; and 
 a word line disposed over a portion of the oxide-free dielectric material, wherein a thickness of the oxide-free dielectric material beneath the word line is greater than a depth difference between the buried gate electrode and the word line. 
 
     
     
       2. The semiconductor structure of  claim 1 , further comprising:
 an isolation disposed over another portion of the oxide-free dielectric material and laterally adjacent to the word line. 
 
     
     
       3. The semiconductor structure of  claim 1 , wherein the oxide-free dielectric material comprises nitride, carbon or a combination thereof. 
     
     
       4. The semiconductor structure of  claim 1 , wherein the gate dielectric layer is further interposed between the oxide-free dielectric material and the word line. 
     
     
       5. The semiconductor structure of  claim 4 , wherein the gate dielectric layer interposed between the buried gate electrode and the first trench is thicker than the gate dielectric layer interposed between the oxide-free dielectric material and the word line. 
     
     
       6. The semiconductor structure of  claim 1 , further comprising:
 a pad oxide layer interposed between the substrate and the oxide-free dielectric material. 
 
     
     
       7. The semiconductor structure of  claim 6 , wherein the pad oxide layer is further interposed between the substrate and the word line. 
     
     
       8. The semiconductor structure of  claim 6 , wherein the oxide-free dielectric material is in contact with the pad oxide layer. 
     
     
       9. The semiconductor structure of  claim 6 , wherein the oxide-free dielectric material is in contact with bottom of the pad oxide layer. 
     
     
       10. The semiconductor structure of  claim 1 , wherein the gate dielectric layer is further disposed on and in contact with the portion of the oxide-free dielectric material. 
     
     
       11. The semiconductor structure of  claim 1 , wherein the non-active region surrounds the active region, and the active region is island-shaped. 
     
     
       12. The semiconductor structure of  claim 1 , wherein the active region has a height higher than a height of the non-active region. 
     
     
       13. The semiconductor structure of  claim 1 , wherein the oxide-free dielectric material comprises silicon nitride. 
     
     
       14. The semiconductor structure of  claim 1 , wherein the oxide-free dielectric material comprises silicon carbon nitride. 
     
     
       15. The semiconductor structure of  claim 1 , wherein the word line is deeper than the buried gate electrode. 
     
     
       16. The semiconductor structure of  claim 1 , further comprising:
 a capping layer over the buried gate electrode and the word line.