Structure of memory device

Abstract

A structure of memory cell includes a substrate. The substrate includes a first active region, a second active region and a first shallow trench isolation (STI) structure between the first active region and the second active region, wherein the first active region is lower than the second active region. A first contact structure is disposed on the first active region. A first stack structure is on the first contact structure. A second contact structure is on the substrate with a bottom portion in the substrate at an interface between the second active region and the first STI structure. A dielectric spacer is at least on a sidewall of the first contact structure. An insulating layer is disposed on the dielectric spacer and between the second contact structure and the first contact structure with the first stack structure, wherein a dielectric constant of the dielectric spacer is lower than a dielectric constant of the insulating layer.

What is claimed is: 
     
       1. A structure of memory cell, comprising:
 a substrate, including a first active region, a second active region and a first shallow trench isolation (STI) structure between the first active region and the second active region, wherein in a cross-section view of the structure of memory cell, a top surface of the first active region is lower than a top surface of the second active region; 
 a first contact structure, disposed on the first active region; 
 a first stack structure on the first contact structure; 
 a second contact structure on the substrate with a bottom portion in the substrate at an interface between the second active region and the first STI structure; 
 a dielectric spacer at least on a sidewall of the first contact structure; and 
 an insulating layer, disposed on the dielectric spacer and between the second contact structure and the first contact structure with the first stack structure, wherein a dielectric constant of the dielectric spacer is lower than a dielectric constant of the insulating layer. 
 
     
     
       2. The structure of memory cell as recited in  claim 1 , wherein the dielectric spacer comprises an oxide spacer or an air spacer and the insulating layer comprises nitride and has a lower portion and an upper portion. 
     
     
       3. The structure of memory cell as recited in  claim 2 , wherein the insulating layer comprises the lower portion comprises a nitride part on the dielectric spacer. 
     
     
       4. The structure of memory cell as recited in  claim 2 , wherein the insulating layer comprises the lower portion comprises a stacked nitride part on the dielectric spacer. 
     
     
       5. The structure of memory cell as recited in  claim 4 , wherein the stacked nitride part comprises a central nitride and a liner nitride on the central nitride, wherein the liner nitride is contact on the dielectric spacer. 
     
     
       6. The structure of memory cell as recited in  claim 2 , wherein insulating layer comprises the upper portion also abuts to the dielectric spacer and is between the first contact structure with the first stack structure and the second contact structure. 
     
     
       7. The structure of memory cell as recited in  claim 6 , wherein the upper portion comprises a nitride part on the dielectric spacer and a sidewall of the first stacked structure. 
     
     
       8. The structure of memory cell as recited in  claim 6 , wherein the upper portion comprises a stack nitride part on the dielectric spacer and a sidewall of the first stacked structure. 
     
     
       9. The structure of memory cell as recited in  claim 8 , wherein the stack nitride part comprises a liner nitride. 
     
     
       10. The structure of memory cell as recited in  claim 8 , wherein the stack nitride part also comprises an air part. 
     
     
       11. The structure of memory cell as recited in  claim 1 , wherein the first contact structure is a bit line contact structure and the second contact structure is a capacitor contact structure. 
     
     
       12. The structure of memory cell as recited in  claim 1 , wherein the first stack layer comprises a conductive stack part at bottom and a mask part at top. 
     
     
       13. The structure of memory cell as recited in  claim 12 , wherein the conductive stack part comprises a barrier layer and a tungsten layer as stacked. 
     
     
       14. The structure of memory cell as recited in  claim 1 , further comprises a second stack structure on the second contact structure. 
     
     
       15. The structure of memory cell as recited in  claim 14 , wherein the second stack structure comprises a CoSix layer, a barrier layer, tungsten layer, and a portion of interconnection structure. 
     
     
       16. The structure of memory cell as recited in  claim 1 , further comprising:
 a second STI structure in the substrate at a side of the second active region; 
 a bit line stack above the second STI structure; and 
 a stack spacer on a sidewall of the bit line stack. 
 
     
     
       17. The structure of memory cell as recited in  claim 16 , wherein the bit line stack comprises, an insulating bottom, a polysilicon layer, a barrier layer, and tungsten as stacked. 
     
     
       18. The structure of memory cell as recited in  claim 17 , wherein the stack spacer comprises an oxide spacer on a sidewall of the polysilicon layer. 
     
     
       19. The structure of memory cell as recited in  claim 18 , wherein the dielectric spacer on the sidewall of the bit line stack also comprises a nitride spacer on the oxide spacer. 
     
     
       20. The structure of memory cell as recited in  claim 16 , wherein the dielectric spacer on the sidewall of the bit line stack comprises a nitride part and an air part in the nitride part, wherein a sidewall of the polysilicon layer is exposed by the air part.