Stack packages including an interconnection structure

Abstract

A stack package includes a package substrate having a bond finger and a stack of a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first pad, a second pad, and a first redistributed line connecting the first and second pads to each other. The second semiconductor die includes a third pad, a fourth pad, and a second redistributed line connecting the third and fourth pads to each other. The first and third pads are connected to each other by a first interconnector which is bonded to the bond finger, and the second and fourth pads are connected to each other by a second interconnector.

What is claimed is: 
     
       1. A stack package comprising:
 a package substrate including a first bond finger; 
 a first semiconductor die disposed on the package substrate, the first semiconductor die including a first pad and a second pad which are spaced apart from each other, and a first redistributed line connecting the first and second pads to each other; 
 a second semiconductor die stacked on the first semiconductor die, the second semiconductor die including a third pad and a fourth pad which are spaced apart from each other, and a second redistributed line connecting the third and fourth pads to each other; 
 a first interconnector disposed to connect the first and third pads to each other and bonded to the first bond finger; and 
 a second interconnector connecting the second and fourth pads to each other, 
 wherein the first bond finger is electrically connected to the third pad through both of a first path and a second path, 
 wherein the first path comprises the first pad and the first interconnector, and 
 wherein the second path is branched from the first interconnector and comprises the first redistributed line, the second pad, the second interconnector, the fourth pad and the second redistributed line. 
 
     
     
       2. The stack package of  claim 1 ,
 wherein each of the first and second interconnectors includes a bonding wire; 
 wherein the package substrate further includes a second bond finger spaced apart from the first bond finger; and 
 wherein the second interconnector extends to be bonded to the second bond finger. 
 
     
     
       3. The stack package of  claim 2 , wherein the first semiconductor die further includes:
 a fifth pad disposed between the first pad and the second pad; 
 a sixth pad located at a side of the second pad opposite to the fifth pad; and 
 a third redistributed line connecting the fifth and sixth pads to each other. 
 
     
     
       4. The stack package of  claim 3 , wherein the second semiconductor die further includes:
 a seventh pad disposed between the third pad and the fourth pad; 
 an eighth pad located at a side of the fourth pad opposite to the seventh pad; and 
 a fourth redistributed line connecting the seventh and eighth pads to each other. 
 
     
     
       5. The stack package of  claim 4 , wherein the package substrate further includes:
 a third bond finger disposed between the first bond finger and the second bond finger; and 
 a fourth bond finger located at a side of the second bond finger opposite to the third bond finger. 
 
     
     
       6. The stack package of  claim 5 , further comprising:
 a third interconnector disposed to connect the fifth and seventh pads to each other and bonded to the third bond finger; and 
 a fourth interconnector disposed to connect the sixth and eighth pads to each other and bonded to the fourth bond finger. 
 
     
     
       7. The stack package of  claim 6 , wherein the third interconnector is an interconnector supplying a ground voltage to the first and second semiconductor dies. 
     
     
       8. The stack package of  claim 3 ,
 wherein the first semiconductor die further includes at least one ninth pad disposed between the second pad and the fifth pad; and 
 wherein the first redistributed line is disposed to circumvent the at least one ninth pad. 
 
     
     
       9. The stack package of  claim 8 , wherein the third redistributed line is located at a side of the at least one ninth pad opposite to the first redistributed line and is disposed to circumvent the at least one ninth pad. 
     
     
       10. The stack package of  claim 9 ,
 wherein the first semiconductor die further includes an additional pad spaced apart from the sixth pad; and 
 wherein the third redistributed line extends to electrically connect the sixth pad to the additional pad. 
 
     
     
       11. The stack package of  claim 9 ,
 wherein the first semiconductor die further includes an additional pad spaced apart from the second pad; and 
 wherein the first redistributed line extends to electrically connect the second pad to the additional pad. 
 
     
     
       12. The stack package of  claim 1 , wherein the first interconnector is an interconnector supplying a power supply voltage to the first and second semiconductor dies. 
     
     
       13. The stack package of  claim 1 , wherein the second semiconductor die is laterally offset relative to the first semiconductor die to provide a step structure and to reveal the first pad, the second pad, and the first redistributed line. 
     
     
       14. A stack package comprising:
 a package substrate including a first bond finger; 
 a first semiconductor die disposed on the package substrate, wherein the first semiconductor die includes a first pad and a second pad which are spaced apart from each other, a plurality of ninth pads disposed between the first and second pads, and a first redistributed line circumventing the plurality of ninth pads to connect the first and second pads to each other; 
 a second semiconductor die stacked on the first semiconductor die, wherein the second semiconductor die includes a third pad and a fourth pad which are spaced apart from each other, a plurality of tenth pads disposed between the third and fourth pads, and a second redistributed line circumventing the plurality of tenth pads to connect the third and fourth pads to each other; 
 a first interconnector disposed to connect the first and third pads to each other and bonded to the first bond finger; and 
 a second interconnector connecting the second and fourth pads to each other, 
 wherein the first bond finger is electrically connected to the third pad through both of a first path and a second path, 
 wherein the first path comprises the first pad and the first interconnector, and 
 wherein the second path is branched from the first interconnector and comprises the first redistributed line, the second pad, the second interconnector, the fourth pad and the second redistributed line. 
 
     
     
       15. The stack package of  claim 14 ,
 wherein each of the first and second interconnectors includes a bonding wire; 
 wherein the package substrate further includes a second bond finger spaced apart from the first bond finger and a plurality of fifth bond fingers disposed between the first and second bond fingers; and 
 wherein the second interconnector extends to be bonded to the second bond finger. 
 
     
     
       16. The stack package of  claim 15 , further comprising a plurality of fifth interconnectors connecting the ninth pads and the tenth pads to the fifth bond fingers. 
     
     
       17. The stack package of  claim 15 , wherein the first semiconductor die further includes:
 a fifth pad disposed between two of the ninth pads located between the first pad and the second pad; 
 a sixth pad located at a side of the second pad opposite to the fifth pad; and 
 a third redistributed line circumventing the second pad and the ninth pads to connect the fifth and sixth pads to each other. 
 
     
     
       18. The stack package of  claim 17 , wherein the second semiconductor die further includes:
 a seventh pad disposed between two of the tenth pads located between the third pad and the fourth pad; 
 an eighth pad located at a side of the fourth pad opposite to the seventh pad; and 
 a fourth redistributed line circumventing the fourth pad and the tenth pads to connect the seventh and eighth pads to each other. 
 
     
     
       19. The stack package of  claim 18 , wherein the package substrate further includes:
 a third bond finger disposed between two of the fifth bond fingers located between the first bond finger and the second bond finger; and 
 a fourth bond finger located at a side of the second bond finger opposite to the third bond finger. 
 
     
     
       20. The stack package of  claim 19 , further comprising:
 a third interconnector disposed to connect the fifth and seventh pads to each other and bonded to the third bond finger; and 
 a fourth interconnector disposed to connect the sixth and eighth pads to each other and bonded to the fourth bond finger. 
 
     
     
       21. The stack package of  claim 20 , wherein the third interconnector is an interconnector supplying a ground voltage to the first and second semiconductor dies. 
     
     
       22. The stack package of  claim 14 , wherein the first interconnector is an interconnector supplying a power supply voltage to the first and second semiconductor dies. 
     
     
       23. The stack package of  claim 14 , wherein the second semiconductor die is laterally offset relative to the first semiconductor die to provide a step structure and to reveal the first pad, the second pad, and the first redistributed line.