Semiconductor structure having a via and methods of manufacturing the same

Abstract

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.

What is claimed is: 
     
       1. A semiconductor structure, comprising:
 a substrate, comprising a base and a composite layer encapsulating the base; 
 a seed layer on the substrate; 
 an epitaxial layer on the seed layer; 
 a semiconductor device on the epitaxial layer; 
 an interlayer dielectric layer on the epitaxial layer and covering the semiconductor device; and 
 a via structure penetrating at least the interlayer dielectric layer, the epitaxial layer, the seed layer and the composite layer and in contact with the base of the substrate. 
 
     
     
       2. The semiconductor structure as claimed in  claim 1 , wherein the via structure comprises a conductive material. 
     
     
       3. The semiconductor structure as claimed in  claim 2 , wherein the composite layer comprises at least two insulating layers and a polysilicon layer between the two insulating layers, wherein the via structure is electrically connected to the polysilicon layer. 
     
     
       4. The semiconductor structure as claimed in  claim 1 , wherein the via structure comprises an insulating material. 
     
     
       5. The semiconductor structure as claimed in  claim 1 , further comprising a patterned metal layer on the interlayer dielectric layer, and the via structure is electrically connected to the patterned metal layer. 
     
     
       6. The semiconductor structure as claimed in  claim 1 , wherein an aspect ratio of the via structure is in a range of 1.6 to 8. 
     
     
       7. The semiconductor structure as claimed in  claim 1 , wherein the base comprises a ceramic material. 
     
     
       8. A method of manufacturing a semiconductor structure, comprising:
 providing a substrate, wherein the substrate comprises a base and a composite layer encapsulating the base; 
 forming a seed layer on the substrate; 
 forming an epitaxial layer on the seed layer; 
 forming a semiconductor device on the epitaxial layer; 
 forming an interlayer dielectric layer on the epitaxial layer, and the interlayer dielectric layer covering the semiconductor device; and 
 forming a via structure that penetrates at least the interlayer dielectric layer, the epitaxial layer, the seed layer and the composite layer, wherein the via structure is in contact with the base of the substrate. 
 
     
     
       9. The method as claimed in  claim 8 , wherein the via structure as formed comprises a conductive material. 
     
     
       10. The method as claimed in  claim 9 , wherein the composite layer comprises at least two insulating layers and a polysilicon layer, and the polysilicon layer is disposed between the two insulating layers, wherein the via structure is electrically connected to the polysilicon layer. 
     
     
       11. The method as claimed in  claim 8 , wherein the via structure comprises an insulating material. 
     
     
       12. The method as claimed in  claim 8 , further comprising forming a patterned metal layer on the interlayer dielectric layer, wherein the via structure is connected to the patterned metal layer. 
     
     
       13. The method as claimed in  claim 8 , wherein forming the via structure that penetrates at least the composite layer comprises:
 forming a first mask layer on the interlayer dielectric layer; 
 forming a second mask layer on the first mask layer; 
 forming a patterned third mask layer on the second mask layer; 
 etching the second mask layer, the first mask layer and interlayer dielectric layer using the patterned third mask layer, so as to form an opening exposing the epitaxial layer; and 
 removing the patterned third mask layer. 
 
     
     
       14. The method as claimed in  claim 13 , wherein the first mask layer, the second mask layer and the patterned third mask layer comprise different materials. 
     
     
       15. The method as claimed in  claim 13 , wherein a first etchant gas is used to etch the second mask layer; and
 a second etchant gas is used to etch the first mask layer and the interlayer dielectric layer, 
 wherein the first etchant gas and the second etchant gas have different fluorocarbon ratios. 
 
     
     
       16. The method as claimed in  claim 13 , wherein after the patterned third mask layer is removed, the method further comprises:
 etching the epitaxial layer and the seed layer along the opening of the second mask layer using the second mask layer as an etch mask, thereby exposing the substrate. 
 
     
     
       17. The method as claimed in  claim 16 , wherein etching the epitaxial layer and the seed layer comprise a plurality of etching steps, and a cleaning step is performed after each of the plurality of etching steps is completed. 
     
     
       18. The method as claimed in  claim 16 , wherein after the opening exposes the substrate, the method further comprises:
 removing the second mask layer by etching, wherein the opening is further extended to penetrate the composite layer and expose the base while the second mask layer is removed; and 
 removing the first mask layer. 
 
     
     
       19. The method as claimed in  claim 18 , wherein the second mask layer is removed by dry etching, and the first mask layer is removed by wet etching.