Semiconductor device

Abstract

A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a chip mounting member; and 
 a semiconductor chip bonded to the chip mounting member through a metal sintered material, 
 wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and 
 wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion not covered by the semiconductor chip is greater than or equal to 15% and less than or equal to 50%, wherein a thickness of the second portion is thicker than a thickness of the first portion. 
 
     
     
       2. The semiconductor device as claimed in  claim 1 , wherein one surface of the second portion in contact with the chip mounting member is parallel to another surface of the second portion opposite the one surface. 
     
     
       3. The semiconductor device as claimed in  claim 1 , further comprising an insulating substrate having an interconnect layer disposed thereon, the interconnect layer being the chip mounting member. 
     
     
       4. The semiconductor device as claimed in  claim 1 , further comprising a lead frame having a die pad, the die pad being the chip mounting member. 
     
     
       5. The semiconductor device as claimed in  claim 1 , wherein an entirety of the first portion has a lower porosity ratio than an entirety of the second portion, a boundary between the first portion and the second portion extending along an entire outer perimeter of the semiconductor chip. 
     
     
       6. The semiconductor device as claimed in  claim 1 , wherein the metal sintered material is a compressed metal sintered material, and the first portion and the second portion are each a compressed metal sintered portion. 
     
     
       7. The semiconductor device as claimed in  claim 1 , wherein the second portion directly covers at least a portion of a lateral surface of the semiconductor chip. 
     
     
       8. The semiconductor device as claimed in  claim 1 , wherein the metal sintered material contains silver or copper. 
     
     
       9. A semiconductor device, comprising:
 a chip mounting member; and 
 a semiconductor chip bonded to the chip mounting member through a metal sintered material, 
 wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, 
 wherein a porosity ratio of the second portion is greater than a porosity ratio of the first portion, and 
 wherein the second portion directly covers at least a portion of a lateral surface of the semiconductor chip, wherein a thickness of the second portion is thicker than a thickness of the first portion. 
 
     
     
       10. The semiconductor device as claimed in  claim 9 , wherein the porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and the porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%. 
     
     
       11. The semiconductor device as claimed in  claim 9 , wherein the metal sintered material contains silver or copper. 
     
     
       12. The semiconductor device as claimed in  claim 9 , wherein one surface of the second portion in contact with the chip mounting member is parallel to another surface of the second portion opposite the one surface. 
     
     
       13. The semiconductor device as claimed in  claim 9 , further comprising an insulating substrate having an interconnect layer disposed thereon, the interconnect layer being the chip mounting member. 
     
     
       14. The semiconductor device as claimed in  claim 9 , wherein an entirety of the first portion has a lower porosity ratio than an entirety of the second portion, a boundary between the first portion and the second portion extending along an entire outer perimeter of the semiconductor chip. 
     
     
       15. The semiconductor device as claimed in  claim 9 , wherein the metal sintered material is a compressed metal sintered material, and the first portion and the second portion are each a compressed metal sintered portion.