Electronic package structure with a core ground wire and chip thereof

Abstract

An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

What is claimed is: 
     
       1. An electronic package structure, comprising:
 a substrate; 
 a chip disposed on and electrically connected to the substrate, wherein a top surface of the chip is disposed with a core wiring region and an input and output pad region, the input and output pad region is located between the core wiring region and an edge of the chip, and the chip includes:
 a plurality of signal pads disposed in the input and output pad region; and 
 a core ground pad disposed in the core wiring region and being adjacent to at least one of the signal pads; 
 
 a plurality of signal wires respectively connected to the signal pads; and 
 a core ground wire connected to the core ground pad, wherein the core ground wire is adjacent to at least one of the signal wires so as to shield the at least one of the signal wires. 
 
     
     
       2. The electronic package structure according to  claim 1 , wherein the chip further includes at least a ground pad, the ground pad and the signal pads are jointly disposed in the input and output pad region and arranged in at least one row along a side of the core wiring region, and the core ground pad is adjacent to one of the signal pads that is the farthest away from the ground pad. 
     
     
       3. The electronic package structure according to  claim 1 , wherein the signal pads are arranged in at least one row along a side of the core wiring region, and the core ground pad is disposed corresponding to two adjacent ones of the signal pads. 
     
     
       4. The electronic package structure according to  claim 3 , further comprising: another core ground wire, wherein the core ground wire and the another core ground wire are both connected to the core ground pad so as to respectively shield two of the signal wires that are adjacent to each other. 
     
     
       5. The electronic package structure according to  claim 1 , wherein the chip further includes a plurality of ground traces and a plurality of power traces, the ground traces and the power traces are alternately arranged in the core wiring region, and the core ground pad is disposed on one of the ground traces. 
     
     
       6. The electronic package structure according to  claim 1 , wherein the input and output pad region includes a plurality of sub-regions that surround the core wiring region, the signal pads are divided into a plurality of pad groups, and each of the pad groups is disposed in the corresponding one of the sub-regions. 
     
     
       7. The electronic package structure according to  claim 6 , wherein the chip further includes:
 a plurality of core ground pads disposed in the core wiring region and near a side of the core wiring region, wherein each of the core ground pads is adjacent to one of the signal pads that is located in the corresponding one of the sub-regions. 
 
     
     
       8. A chip comprising:
 a core wiring region disposed at a top surface of the chip; 
 an input and output pad region disposed at the top surface of the chip and located between the core wiring region and an edge of the chip; 
 a plurality of signal pads disposed in the input and output pad region; 
 a core ground pad disposed in the core wiring region and adjacent to one of the signal pads; and 
 at least one ground pad, wherein the at least one ground pad and the signal pads are disposed in the input and output pad region and arranged in at least one row along a side of the core wiring region; 
 wherein the core ground pad is adjacent to one of the signal pads that is the farthest away from the ground pad. 
 
     
     
       9. The chip according to  claim 8 , further comprising a plurality of ground traces and a plurality of power traces, wherein the ground traces and the power traces are alternately arranged in the core wiring region, and the core ground pad is disposed on one of the ground traces. 
     
     
       10. The chip according to  claim 8 , wherein the input and output pad region includes a plurality of sub-regions that surround the core wiring region, the signal pads are divided into a plurality of pad groups, and each of the pad groups is arranged in the corresponding one of the sub-regions. 
     
     
       11. The chip according to  10 , further comprising: a plurality of other core ground pads disposed in the core wiring region and near sides of the core wiring region, wherein the core ground pad and the other core ground pads are each adjacent to the corresponding one of the signal pads that is located in the corresponding one of the sub-regions. 
     
     
       12. The chip according to  claim 8 , further comprising: another core ground pad disposed in the core wiring region, and an area occupied by the core ground pad is different from an area occupied by the another ground pad. 
     
     
       13. A chip comprising:
 a core wiring region disposed at a top surface of the chip; 
 an input and output pad region disposed at the top surface of the chip and located between the core wiring region and an edge of the chip; 
 a plurality of signal pads disposed in the input and output pad region; 
 a core ground pad disposed in the core wiring region and adjacent to one of the signal pads; and 
 a plurality of ground traces and a plurality of power traces, wherein the ground traces and the power traces are alternately arranged in the core wiring region, and the core ground pad is disposed on one of the ground traces.