Programming techniques including an all string verify mode for single-level cells of a memory device

Abstract

A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.

What is claimed is: 
     
       1. A storage device, comprising:
 a block including a plurality of memory cells; and 
 a circuit coupled to the plurality of memory cells of the block and configured to:
 program a plurality of memory cells of a plurality of strings of a word line of the block using single pulse programming to store only a single bit of data in each memory cell; 
 verify in parallel, for a plurality of sets of the memory cells, a data state of a set of the memory cells, wherein each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line; 
 determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state; and 
 determine, based on the number of sets that are in the first data state, whether the block is faulty. 
 
 
     
     
       2. The storage device as set forth in  claim 1 , wherein the circuit is further configured to:
 program randomly generated data into memory cells of the plurality of strings of the word line of the block, the randomly generated data indicating that a portion of the memory cells of the plurality of strings is assigned to represent the first data state and a remainder of the memory cells of the plurality of strings is assigned to represent a second data state. 
 
     
     
       3. The storage device as set forth in  claim 1 , wherein the first data state is a programmed data state. 
     
     
       4. The storage device as set forth in  claim 1 , wherein each memory cell of the set of the memory cells is connected to a same bit line. 
     
     
       5. The storage device as set forth in  claim 1 , wherein the circuit is further configured to:
 count, in a first tier of the word line, the number of sets of the plurality of memory cell sets that are in the first data state. 
 
     
     
       6. The storage device as set forth in  claim 1 , wherein the circuit is further configured to:
 determine the block is faulty if the number of sets that are in the first data state is below a threshold. 
 
     
     
       7. A method of operating a memory apparatus including a plurality of memory cells, the method comprising the steps of:
 programming a plurality of memory cells of a plurality of strings of a word line of a block using single pulse programming to store only a single bit of data in each memory cell; 
 verifying in parallel, for a plurality of sets of the memory cells, a data state of a set of the memory cells, wherein each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line; 
 determining a number of sets of the plurality of memory cell sets that are verified to be in a first data state; and 
 determining, based on the number of sets that are in the first data state, whether the block is faulty. 
 
     
     
       8. The method as set forth in  claim 7 , further including the steps of:
 programming randomly generated data into memory cells of the plurality of strings of the word line of the block, the randomly generated data indicating that a portion of the memory cells of the plurality of strings is assigned to represent the first data state and a remainder of the memory cells of the plurality of strings is assigned to represent a second data state. 
 
     
     
       9. The method as set forth in  claim 7 , wherein the first data state is a programmed data state. 
     
     
       10. The method as set forth in  claim 7 , wherein each memory cell of the set of the memory cells is connected to a same bit line. 
     
     
       11. The method as set forth in  claim 7 , wherein the circuit is further configured to:
 count, in a first tier of the word line, the number of sets of the plurality of memory cell sets that are in the first data state. 
 
     
     
       12. The method as set forth in  claim 7 , further including the steps of:
 determining the block is faulty if the number of sets that are in the first data state is below a threshold. 
 
     
     
       13. A controller in communication with a plurality of memory cells of a memory apparatus, the controller configured to:
 instruct the memory apparatus to program a plurality of memory cells of a plurality of strings of a word line of a block using single pulse programming to store only a single bit of data in each memory cell; 
 instruct the memory apparatus to verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, wherein each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line; 
 instruct the memory apparatus to determine, based on the number of sets, whether the block is faulty; and 
 receive a notification as to whether the block is faulty. 
 
     
     
       14. The controller as set forth in  claim 13 , wherein the controller is further configured to:
 instruct the memory apparatus to program randomly generated data into memory cells of the plurality of strings of the word line of the block, the randomly generated data indicating that a portion of the memory cells of the plurality of strings is assigned to represent the first data state and a remainder of the memory cells of the plurality of strings is assigned to represent a second data state. 
 
     
     
       15. The controller as set forth in  claim 13 , wherein the first data state is a programmed data state. 
     
     
       16. The controller as set forth in  claim 13 , wherein each memory cell of the set of the memory cells is connected to a same bit line. 
     
     
       17. The controller as set forth in  claim 13 , wherein the controller is further configured to:
 instruct the memory apparatus to count, in a first tier of the word line, the number of sets of the plurality of memory cell sets that are in the first data state.