Metal gates and manufacturing methods thereof

Abstract

A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

What is claimed is: 
     
       1. A method, comprising:
 forming an interfacial layer over a semiconductor layer; 
 depositing a high-k dielectric layer over the interfacial layer; 
 forming a dummy gate electrode over the high-k dielectric layer; 
 patterning the dummy gate electrode, the high-k dielectric layer, and the interfacial layer, resulting in the interfacial layer to extend laterally beyond outer edges of the high-k dielectric layer and the high-k dielectric layer to extend laterally beyond outer edges of the dummy gate electrode; 
 forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer; 
 forming source/drain features adjacent to the spacers; and 
 replacing the dummy gate electrode with a metal gate electrode. 
 
     
     
       2. The method of  claim 1 , further comprising, after depositing the high-k dielectric layer and before forming the dummy gate electrode, performing a spike anneal process. 
     
     
       3. The method of  claim 1 , further comprising, before replacing the dummy gate electrode, forming a silicide layer on the source/drain features, such that the silicide layer wraps around portions of the source/drain features. 
     
     
       4. The method of  claim 1 , wherein replacing the dummy gate electrode includes:
 removing the dummy gate electrode to form a trench; 
 forming a work function metal layer in the trench, such that sidewall portions of the work function metal layer contact the spacers and a bottom portion of the work function metal layer contacts the high-k dielectric layer; and 
 forming a bulk conductive layer over the work function metal layer. 
 
     
     
       5. The method of  claim 1 , further comprising forming doped regions below the dummy gate electrode in the semiconductor layer before forming the spacers. 
     
     
       6. The method of  claim 1 , further comprising forming a capping layer on the high-k dielectric layer before forming the dummy gate electrode, wherein replacing the dummy gate electrode removes the capping layer. 
     
     
       7. The method of  claim 6 , further comprising performing a spike anneal process to the capping layer in a nitrogen environment before forming the dummy gate electrode. 
     
     
       8. A method, comprising:
 forming an interfacial layer over a fin, the fin being oriented in a first direction; 
 depositing a high-k dielectric layer over the interfacial layer; 
 depositing a polysilicon layer over the high-k dielectric layer, the polysilicon layer being oriented in a second direction generally perpendicular to the first direction; 
 patterning the polysilicon layer, the high-k dielectric layer, and the interfacial layer, such that portions of the interfacial layer extend beyond outer edges of the high-k dielectric layer along the first direction; 
 forming gate spacers on sidewalls of the polysilicon layer, wherein portions of the gate spacers are formed over the extended portions of the interfacial layer; 
 forming source/drain features in the fin; 
 forming a silicide layer over the source/drain features, wherein the silicide layer wraps around portions of the source/drain features; 
 removing the polysilicon layer to form a trench; and 
 forming a metal gate over the high-k dielectric layer in the trench. 
 
     
     
       9. The method of  claim 8 , wherein the patterning of the polysilicon layer, the high-k dielectric layer, and the interfacial layer includes:
 forming an etch mask over a portion of the polysilicon layer; and 
 performing an etching process to remove portions of the polysilicon layer exposed by the etch mask, resulting in a patterned polysilicon layer having slanted sidewalls. 
 
     
     
       10. The method of  claim 9 , wherein the etching process selectively removes portions of the interfacial layer, the high-k dielectric layer, or both. 
     
     
       11. The method of  claim 8 , further comprising, after depositing the high-k dielectric layer and before forming the polysilicon layer:
 annealing the high-k dielectric layer; 
 depositing a titanium-containing capping layer over the annealed high-k dielectric layer; and 
 annealing the titanium-containing capping layer. 
 
     
     
       12. The method of  claim 11 , wherein removing the polysilicon layer removes the titanium-containing capping layer to expose the high-k dielectric layer. 
     
     
       13. The method of  claim 8 , further comprising forming an interlayer dielectric (ILD) layer over the silicide layer before removing the polysilicon layer. 
     
     
       14. A semiconductor structure, comprising:
 a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, the HKMG including:
 an interfacial layer disposed over the semiconductor layer, the interfacial layer having a first length along a first direction; 
 a high-k dielectric layer disposed over the interfacial layer, the high-k dielectric layer having a second length along the first direction, wherein the second length is less than the first length; and 
 a gate electrode disposed over the high-k dielectric layer, the gate electrode having a third length along the first direction, wherein the second length is greater than the third length, and wherein outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile; 
 
 gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer; and 
 source/drain features disposed in the semiconductor layer adjacent to the HKMG. 
 
     
     
       15. The semiconductor structure of  claim 14 , further comprising a silicide layer wrapping around upper portions of the source/drain features. 
     
     
       16. The semiconductor structure of  claim 15 , further comprising an interlayer dielectric (ILD) layer disposed over the silicide layer and a source/drain contact disposed in the ILD layer to contact the silicide layer. 
     
     
       17. The semiconductor structure of  claim 14 , wherein sidewall portions of the gate spacers are free of the high-k dielectric layer. 
     
     
       18. The semiconductor structure of  claim 16 , wherein the silicide layer spans a first width along a second direction substantially perpendicular to the first direction and the source/drain contact spans a second width along the second direction, the first width being greater than the second width. 
     
     
       19. The semiconductor structure of  claim 14 , wherein a distance between an outer edge of the gate electrode and an outer edge of the high-k dielectric layer is less than a distance between the outer edge of the gate electrode and an outer edge of the interfacial layer. 
     
     
       20. The semiconductor structure of  claim 14 , wherein each sidewall of the gate electrode forms an acute angle with the high-k dielectric layer.