Look-up table read

Abstract

A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

What is claimed is: 
     
       1. A digital data processor comprising:
 an instruction memory configured to store instructions; 
 an instruction decoder coupled to the instruction memory configured to sequentially recall and decode the instructions from the instruction memory; 
 a memory configured to store tables; 
 an intermediate register coupled to the memory; 
 a butterfly network coupled to the intermediate register; 
 a data register file that includes a destination register; and 
 at least one operational unit coupled to the data register file and to the instruction decoder and configured to:
 perform a data processing operation based on an instruction decoded by the instruction decoder and store results of the data processing operation; and 
 perform a table recall in response to a look up table read instruction that specifies the tables, a respective location in each of the tables, and the destination register by, for each of the tables:
 recalling, from the memory, a first data element stored at the respective location and a second data element stored at an adjacent location; 
 causing the first data element and the second data element to be stored in the intermediate register in a first order; 
 causing the butterfly network to reorder the first data element and the second data element to be in a second order; 
 and 
 causing the first data element and the second data element to be stored in the second order in successive slots in the destination register such that the first data element and the second data element include an extension of a number of elements based on a scaled promotion type. 
 
 
 
     
     
       2. The digital data processor of  claim 1 , wherein:
 the data register file includes a plurality of data registers designated by register number, each data register storing data; 
 the look up table read instruction includes a destination operand field specifying a register number of one of the data registers in the data register file; and 
 the instruction decoder is configured to decode the look up table read instruction to identify the data register having the register number of the destination operand field as the destination register. 
 
     
     
       3. The digital data processor of  claim 2 , wherein:
 the look up table read instruction includes a source operand field specifying a register number of a source index register in the data register file; and 
 the instruction decoder is configured to decode the look up table read instruction to determine the respective location in each of the tables based on the source index register having the register number. 
 
     
     
       4. The digital data processor of  claim 3 , wherein:
 the look up table read instruction specifies a look up table base address register storing a table base address; and 
 the instruction decoder is configured to decode the look up table read instruction to determine the tables based on the table base address stored in the look up table base address register. 
 
     
     
       5. The digital data processor of  claim 1 , wherein the look up table read instruction specifies a look up table configuration register having a look up table data element size field that indicates a data size of the first data element and the second data element. 
     
     
       6. The digital data processor of  claim 5 , wherein the look up table configuration register includes an interpolation field specifying a number of data elements of the specified data size to be recalled in addition to the first data element at the respective location. 
     
     
       7. The digital data processor of  claim 6 , wherein the interpolation field is configured to indicate a number of data elements selected from one of no interpolation, 2 element interpolation, 4-element interpolation, and 8-element interpolation. 
     
     
       8. The digital data processor of  claim 5 , wherein the look up table configuration register includes a table size field specifying a size of each of the tables. 
     
     
       9. The digital data processor of  claim 5 , wherein the look up table configuration register includes a field specifying a number of tables of a table set. 
     
     
       10. The digital data processor of  claim 1 , further comprising:
 a level one data memory comprising: 
 a first portion including a level one data cache coupled to the at least one operational unit, wherein the first portion is configured to store data for manipulation by the at least one operational unit, wherein the level one data cache services memory reads and writes of the least one operational unit; and 
 a second portion including memory directly accessible via the at least one operational unit, wherein the tables are stored in the second portion of the level one data memory. 
 
     
     
       11. The digital data processor of  claim 1 , wherein the memory includes a set of banks and the first order is based on an arrangement of elements of the tables within the set of banks. 
     
     
       12. The digital data processor of  claim 1 , wherein each of the tables includes a respective set of columns and the first order is based on an arrangement of elements in the respective set of columns. 
     
     
       13. A method, comprising:
 storing, for each table of a set of tables stored in a memory, a respective index in a source index register of a data register file; and 
 performing, by an operational unit coupled to the memory and the data register file, a table recall in response to a look up table read instruction by, for each table of the set of tables:
 recalling, from the memory, a first data element stored at the respective index and a second data element stored at an adjacent index; 
 storing the first data element and the second data element in an intermediate register in a first order; 
 reordering the first data element and the second data element using a butterfly network to be in a second order; and 
 storing the first data element and the second data element in successive slots in a destination register of the data register file in the second order such that the first data element and the second data element, include an extension of a number of elements based on a scaled promotion type. 
 
 
     
     
       14. The method of  claim 13 , wherein:
 the data register file includes a plurality of data registers designated by register number, each data register storing data; and 
 the look up table read instruction includes a destination operand field specifying a register number of one of the data registers in the data register file. 
 
     
     
       15. The method of  claim 14 , wherein the look up table read instruction includes a source operand field specifying a register number of a source index register in the data register file, the method further comprising:
 decoding, by an instruction decoder, the look up table read instruction to determine the respective index in each of the set of tables based on the source index register. 
 
     
     
       16. The method of  claim 15 , wherein the look up table read instruction specifies a look up table base address register storing a table base address, the method further comprising:
 decoding, by the instruction decoder, the look up table read instruction to determine the set of tables based on the table base address stored in the look up table base address register. 
 
     
     
       17. The method of  claim 13 , wherein the look up table read instruction specifies a look up table configuration register having a look up table data element size field that indicates a data size of the first data element and the second data element. 
     
     
       18. The method of  claim 17 , wherein the look up table configuration register includes an interpolation field specifying a number of data elements of the specified data size to be recalled in addition to the first data element at the respective index. 
     
     
       19. The method of  claim 18 , wherein the interpolation field is configured to indicate a number of data elements selected from one of no interpolation, 2-element interpolation, 4-element interpolation, and 8-element interpolation. 
     
     
       20. The method of  claim 17 , wherein the look up table configuration register includes a table size field specifying a size of each table of the set of tables. 
     
     
       21. The method of  claim 17 , wherein the look up table configuration register includes a field specifying a number of tables of a table set.