Inventor

BHORIA NAVEEN

US107 patents

⚠️ This page may combine multiple inventors who share the name “BHORIA NAVEEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHORIA NAVEEN

TEXAS INSTRUMENTS INC

Highly integrated scalable, flexible DSP megamodule architecture

Highly integrated scalable, flexible DSP megamodule architecture

Methods and apparatus to reduce bank pressure using aggressive write merging

Methods and apparatus to facilitate read-modify-write support in a victim cache

Look-up table initialize

Methods and apparatus to facilitate an atomic operation and/or a histogram operation in cache pipeline

Methods and apparatus for allocation in a victim cache system

Methods and apparatus to facilitate atomic operations in victim cache

Methods and apparatus for multi-banked victim cache with dual datapath

Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system

Highly integrated scalable, flexible DSP megamodule architecture

Methods and apparatus to facilitate write miss caching in cache system

Methods and apparatus to reduce bank pressure using aggressive write merging

Look-up table initialize

Look-up table write

Look-up table write

Methods and apparatus to reduce read-modify-write cycles for non-aligned writes

Methods and apparatus for allocation in a victim cache system

Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system

Methods and apparatus to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding

Methods and apparatus to facilitate write miss caching in cache system

Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue

Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths

Look-up table read

Methods and apparatus for eviction in dual datapath victim cache system

Victim cache with write miss merging

Histogram operation

Zero cycle clock invalidate operation

Cache size change

Global coherence operations

Look up table with data element promotion

Tag update bus for updated coherence state

Programmable address-based write-through cache control

Methods and apparatus to reduce read-modify-write cycles for non-aligned writes

Victim cache that supports draining write-miss entries

Write merging on stores with different tags

Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths

Victim cache with write miss merging

Hardware coherence for memory controller

Methods and apparatus to facilitate atomic operations in victim cache

Look-up table write

Write merging on stores with different privilege levels

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Look-up table initialize

Atomic compare and swap in a coherent cache system

Aggressive write flush scheme for a victim cache

Hardware coherence signaling protocol

DAMODARAN RAGURAM

Requester based transaction status reporting in a system with multi-level memory

Memory attribute sharing between differing cache levels of multilevel cache