Magnetoresistive random access memory and method for fabricating the same

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.

What is claimed is: 
     
       1. A method for fabricating a semiconductor device, comprising:
 providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region; 
 forming a magnetic tunneling junction (MTJ) on the MRAM region; 
 forming a metal interconnection on the MTJ; 
 forming a stop layer on the metal interconnection; and 
 forming a blocking layer on the stop layer. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming a first dielectric layer on the blocking layer; and 
 forming a second dielectric layer on the first dielectric layer. 
 
     
     
       3. The method of  claim 2 , wherein the first dielectric layer comprises silicon oxide. 
     
     
       4. The method of  claim 2 , wherein the blocking layer comprises metal. 
     
     
       5. The method of  claim 4 , wherein the blocking layer comprises aluminum. 
     
     
       6. The method of  claim 1 , further comprising:
 forming a first dielectric layer on the metal interconnection; and 
 forming the blocking layer on the first dielectric layer. 
 
     
     
       7. The method of  claim 6 , wherein the first dielectric layer comprises silicon oxide. 
     
     
       8. The method of  claim 6 , wherein the blocking layer comprises a second dielectric layer. 
     
     
       9. The method of  claim 8 , wherein the blocking layer comprises silicon carbide, silicon carbon nitride (SiCN), or silicon carbo-oxynitride (SiCON). 
     
     
       10. The method of  claim 1 , further comprising performing a high pressure anneal process after forming the blocking layer. 
     
     
       11. A semiconductor device, comprising:
 a substrate having a logic region and a magnetoresistive random access memory (MRAM) region; 
 a MTJ on the MRAM region; 
 a metal interconnection on the MTJ; 
 a stop layer on the metal interconnection; and 
 a blocking layer on the stop layer. 
 
     
     
       12. The semiconductor device of  claim 11 , further comprising:
 a first dielectric layer on the blocking layer; and 
 a second dielectric layer on the first dielectric layer. 
 
     
     
       13. The semiconductor device of  claim 12 , wherein the first dielectric layer comprises silicon oxide. 
     
     
       14. The semiconductor device of  claim 12 , wherein the blocking layer comprises metal. 
     
     
       15. The semiconductor device of  claim 14 , wherein the blocking layer comprises aluminum. 
     
     
       16. The semiconductor device of  claim 11 , further comprising:
 a first dielectric layer on the metal interconnection; and 
 the blocking layer on the first dielectric layer. 
 
     
     
       17. The semiconductor device of  claim 16 , wherein the first dielectric layer comprises silicon oxide. 
     
     
       18. The semiconductor device of  claim 16 , wherein the blocking layer comprises a second dielectric layer. 
     
     
       19. The semiconductor device of  claim 18 , wherein the blocking layer comprises silicon carbide, silicon carbon nitride (SiCN), or silicon carbo-oxynitride (SiCON). 
     
     
       20. The semiconductor device of  claim 11 , wherein the blocking layer comprises a grid line pattern according to a top view.