Memory device with air gaps for reducing capacitive coupling

Abstract

The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.

What is claimed is: 
     
       1. A memory device, comprising:
 a substrate, having a first active region and a second active region; 
 a word line, formed in the substrate and intersected with the first and second active regions; 
 a first conductive pillar and a second conductive pillar, disposed over the substrate, and overlapped with and electrically connected to the first and second active regions, respectively, wherein the first and second conductive pillars are arranged along a direction substantially parallel to an extending direction of the word line; 
 a first landing pad and a second landing pad, disposed on the first and second conductive pillars, and overlapped with and electrically connected to the first and second conductive pillars, respectively, wherein sidewalls of the first and second conductive pillars are recessed from sidewalls of the first and second landing pads, wherein the first and second landing pads and the first and second conductive pillars are respectively made of different conductive materials, and a resistivity of the first and second landing pads is lower than a resistivity of the first and second conductive pillars; and 
 a dielectric layer, laterally surrounding the first and second conductive pillars as well as the first and second landing pads, and having an air gap between the first and second conductive pillars. 
 
     
     
       2. The memory device according to  claim 1 , wherein the first and second conductive pillars as well as the first and second landing pads are located at the same side of the word line. 
     
     
       3. The memory device according to  claim 1 , wherein a space between the first and second landing pads is sealed by the dielectric layer. 
     
     
       4. The memory device according to  claim 1 , wherein a footprint area of the first landing pad is greater than a footprint area of the first conductive pillar, and a footprint area of the second landing pad is greater than a footprint area of the second conductive pillar. 
     
     
       5. The memory device according to  claim 1 , wherein a lateral distance between the first and second landing pads is shorter than a lateral distance between the first and second conductive pillars. 
     
     
       6. The memory device according to  claim 1 , wherein
 the first landing pad is offset from the second landing pad toward a direction perpendicular to the extending direction of the word line. 
 
     
     
       7. The memory device according to  claim 1 , further comprising:
 a first contact structure and a second contact structure, disposed between the substrate and the first and second conductive pillars, wherein the first contact structure is electrically connected to and overlapped with the first active region and the first conductive pillar, and the second contact structure is electrically connected to and overlapped with the second active region and the second conductive pillar. 
 
     
     
       8. The memory device according to  claim 1 , further comprising:
 a first capacitor plug and a second capacitor plug, disposed on and electrically connected to the first and second landing pads, respectively; and 
 a first storage capacitor and a second capacitor, disposed on and electrically connected to the first and second capacitor plugs, respectively. 
 
     
     
       9. The memory device according to  claim 8 , wherein a footprint area of the first landing pad is greater than a footprint area of the first capacitor plug, and a footprint area of the second landing pad is greater than a footprint area of the second capacitor plug. 
     
     
       10. A memory device, comprising:
 a substrate, having an active region; 
 an isolation structure, formed in the substrate and laterally surrounding the active region; 
 a word line, formed in the substrate and intersected with the active region; 
 a bit line, extending above the substrate and electrically connected to the active region; 
 a conductive pillar, disposed over the substrate and electrically connected to the active region, wherein the bit line and the conductive pillar are located at opposite sides of the word line, and a top surface of the bit line is aligned with or lower than a bottom surface of the conductive pillar; 
 a landing pad, disposed on and electrically connected to the conductive pillar, wherein a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad, and wherein the landing pad and the conductive pillar are respectively made of different conductive materials, and a resistivity of the landing pad is lower than a resistivity of the conductive pillar; and 
 a storage capacitor, disposed over and electrically connected to the landing pad. 
 
     
     
       11. The memory device according to  claim 10 , further comprising:
 a first contact structure, extending between and electrically connected to the active region and the bit line; and 
 a second contact structure, extending between and electrically connected to the active region and the conductive pillar. 
 
     
     
       12. The memory device according to  claim 11 , wherein the first contact structure is shorter than the second contact structure. 
     
     
       13. The memory device according to  claim 10 , wherein a footprint area of the landing pad is greater than a footprint area of the conductive pillar. 
     
     
       14. The memory device according to  claim 10 , wherein an extending direction of the word line is intersected with an extending direction of the bit line and an extending direction of the active region.