Controlling test networks of chips using integrated processors

Abstract

The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

What is claimed is: 
     
       1. A chip, comprising:
 a chiplet including at least one test network; 
 at least one external connector; and 
 a test processor connected to and positioned between the at least one test network and the at least one external connector, wherein the test processor is configured to control the at least one test network for testing of the chiplet. 
 
     
     
       2. The chip as recited in  claim 1 , further comprising an interface block configured to receive and provide test data and configuration data to the test processor for controlling the at least one test network for the testing. 
     
     
       3. The chip as recited in  claim 2 , the at least one external connector is configured to receive the test data and configuration data from an external source and provide the test data and configuration data to the interface block. 
     
     
       4. The chip as recited in  claim 3 , wherein the at least one external connector is a high speed link interconnect, a memory pin, or a chip connector. 
     
     
       5. The chip as recited in  claim 3 , wherein the processor is connected to the at least one test network via a high speed link. 
     
     
       6. The chip as recited in  claim 1 , wherein the chiplet includes multiple test networks and the test processor is configured to control each of the multiple test networks to test the chiplet. 
     
     
       7. The chip as recited in  claim 1 , wherein the chiplet further includes a custom controller for the at least one test network and the test processor is configured to control the at least one test network for the testing via the custom controller. 
     
     
       8. The chip as recited in  claim 1 , wherein the test processor is a master processor for the chiplet. 
     
     
       9. The chip as recited in  claim 8 , wherein the chip further includes a top level processor that directs test data and configuration data to the at least one test network via the master processor. 
     
     
       10. The chip as recited in  claim 9 , wherein the chiplet is a first chiplet and the chip includes a second chiplet having at least one testing network and the top level processor is configured to control the at least one testing network for testing of the second chiplet. 
     
     
       11. The chip as recited in  claim 10 , wherein the master processor is a first master processor and the second chiplet further includes a second master processor, and the top level processor is configured to control the at least one testing network via the second master processor. 
     
     
       12. The chip as recited in  claim 1 , wherein the processor is a top level processor for the chip. 
     
     
       13. A multi-chip processing system, comprising:
 a first chip including at least one external connector, a first chiplet having at least one test network, a first connection fabric, and a first processor configured to control the at least one test network for testing of the first chiplet, wherein the first processor is connected to the at least one test network via the first connection fabric and is positioned between the at least one external connector and the at least one test network; and 
 a second chip including a second chiplet having at least one testing network, a second connection fabric, and a second processor configured to control the at least one testing network for testing of the second chiplet, wherein the second processor is connected to the at least one testing network via the second connection fabric, and the first and second chips are connected via the first and second connection fabrics. 
 
     
     
       14. The multi-chip processing system as recited in  claim 13 , wherein the first processor is a system master processor for the multi-chip processing system that configures the second processor for controlling the at least one testing network. 
     
     
       15. The multi-chip processing system as recited in  claim 14 , wherein the second processor is a master processor for the second chiplet. 
     
     
       16. The multi-chip processing system as recited in  claim 14 , wherein the system master processor receives test data and configuration data via an interface block connected to the at least one external connector of the first chip, and the first and second connection fabrics are high speed links that each include at least one router. 
     
     
       17. The multi-chip processing system as recited in  claim 13 , wherein the multi-chip processing system is a stacked die configuration. 
     
     
       18. The multi-chip processing system as recited in  claim 13 , wherein the first and second fabrics are connected together via an interposer. 
     
     
       19. A method of designing a chip, comprising:
 receiving a system level design for the chip, wherein the chip includes at least one external connector; 
 converting the system level design to a register transfer level description and inserting therein a register transfer level description of test networks and at least one test processor that is programmable for interfacing and controlling the test networks; and 
 creating a physical design for the chip employing the register transfer level description that includes the test networks and the at least one test processor, wherein the at least one test processor is positioned between the at least one external connector and the test networks. 
 
     
     
       20. The method as recited in  claim 19 , wherein the creating includes making low-level test-network connections based on the physical design. 
     
     
       21. A graphics processing unit (GPU) chip; comprising:
 a plurality of chiplets, wherein one or more of the plurality of chiplets includes at least one test network and two or more of the plurality of chiplets are configured to perform graphics computations; and 
 a hierarchy of test processors connected to and configured to control the at least one test network for testing of the plurality of chiplets, wherein the hierarchy of test processors are positioned between the at least one test network and an external connector of the GPU chip. 
 
     
     
       22. The GPU chip as recited in  claim 21 , wherein the hierarchy of test processors includes a top level processor configured to direct test data and configuration data to the at least one test network of the plurality of chiplets. 
     
     
       23. The GPU chip as recited in  claim 22 , wherein the hierarchy of test processors further includes a master processor of one or more of the plurality of chiplets. 
     
     
       24. The GPU chip as recited in  claim 21 , wherein one or more of the plurality of chiplets include multiple test networks and the hierarchy of test processors directs test data and configuration data to the multiple test networks of the plurality of chiplets. 
     
     
       25. A system on a chip (SoC); comprising:
 at least one graphics processing unit (GPU) chip including a first external connector, a first plurality of chiplets that each have at least one test networks, a first connection fabric, and a first processor configured to control each of the at least one test networks for testing a respective one of the first plurality of chiplets, wherein the first processor is connected to each of the at least one test networks via the first connection fabric and is positioned between the first external connector and each of the at least one test networks; and 
 at least one central processing unit (CPU) chip including a second plurality of chiplets that each have at least one testing networks, a second connection fabric, and a second processor configured to control each of the at least one testing networks for testing a respective one of the second plurality of chiplets, wherein the second processor is connected to each of the at least one testing networks via the second connection fabric. 
 
     
     
       26. The SoC as recited in  claim 25 , wherein the CPU chip includes a second external connector, and the first and second connection fabrics are connected via the first and second external connectors. 
     
     
       27. The SoC as recited in  claim 25 , wherein one or more of the first plurality of chiplets and one or more of the second plurality of chiplets further include a master processor, wherein the first processor, the second processor, and the master processor are hierarchically ordered.