Storage device, multi-component device and method of controlling operation of the same

Abstract

A storage device includes a solid state drive (SSD), a field programmable gate array (FPGA), a power sensor and a global controller. The SSD stores data and receives power through a power rail connected to a host device. The FPGA processes data read from the SSD or data to be stored in the SSD and receives power through the power rail. The power sensor is connected to the power rail and generates a measured power value corresponding to a total power consumed by the SSD and the FPGA by measuring the total power. The global controller determines one of the SSD and the FPGA as a priority component operating with a fixed performance and determines the other of the SSD and the FPGA as a non-priority component operating with a variable performance in a priority mode based on power control information provided from the host device.

What is claimed is: 
     
       1. A storage device comprising:
 a solid state drive (SSD) configured to store data and receive power through a power rail connected to a host device; 
 a field programmable gate array (FPGA) configured to process data read from the SSD or data to be stored in the SSD and receive power through the power rail; 
 a power sensor connected to the power rail and configured to generate a measured power value corresponding to a total power consumed by the SSD and the FPGA by measuring the total power; and 
 a global controller configured to determine one of the SSD and the FPGA as a priority component operating with a fixed performance and determine another of the SSD and the FPGA as a non-priority component operating with a variable performance in a priority mode based on power control information provided from the host device. 
 
     
     
       2. The storage device of  claim 1 , wherein the power control information provided from the host device includes a target power value indicating a power limit of the storage device, priority component information indicating the priority component and a target performance value indicating the fixed performance of the priority component. 
     
     
       3. The storage device of  claim 2 , wherein the priority component operates with the fixed performance in the priority mode based on the target performance value regardless of the measured power value. 
     
     
       4. The storage device of  claim 3 , wherein the non-priority component operates with the variable performance in the priority mode based on the target power value and the measured power value such that the total power does not exceed the power limit. 
     
     
       5. The storage device of  claim 2 , wherein:
 the global controller determines each of the SSD and the FPGA as the non-priority component in a non-priority mode, and 
 each of the SSD and FPGA operates with the variable performance in the non-priority mode based on the target power value and the measured power value such that the total power does not exceed the power limit. 
 
     
     
       6. The storage device of  claim 5 , wherein the global controller monitors whether the total power exceeds the power limit based on the target power value and the measured power value, and when the total power exceeds the power limit in the priority mode, the global controller converts from the priority mode to an adaptive mode in which the target power value is changed. 
     
     
       7. The storage device of  claim 6 , wherein the global controller adjusts the target power value periodically with a power adjustment period based on an average power value indicating an average of the total power during a time window. 
     
     
       8. The storage device of  claim 7 , wherein:
 the global controller sequentially decreases the target power value with the power adjustment period when the total power exceeds the power limit in the adaptive mode and converts from the adaptive mode to the non-priority mode by determining each of the SSD and the FPGA as the non-priority component when the target power value is decreased to be lower than a low limit value, and 
 each of the SSD and FPGA operates with the variable performance in the non-priority mode based on the target power value and the measured power value such that the total power does not exceed the power limit. 
 
     
     
       9. The storage device of  claim 2 , wherein:
 the SSD includes: 
 a first fixed performance controller configured to, based on the target performance value, generate a first fixed performance control value to control the fixed performance of the SSD; and 
 a first variable performance controller configured to, based on the target power value and the measured power value, generate a first variable performance control value to control the variable performance of the SSD such that the total power does not exceed the power limit, and 
 the FPGA includes: 
 a second fixed performance controller configured to, based on the target performance value, generate a second fixed performance control value to control the fixed performance of the FPGA; and 
 a second variable performance controller configured to, based on the target power value and the measured power value, generate a second variable performance control value to control the variable performance of the FPGA such that the total power does not exceed the power limit. 
 
     
     
       10. The storage device of  claim 9 , wherein each of the first variable performance controller and the second variable performance controller includes a proportional-integral-differential (PID) controller configured to generate each of the first variable performance control value and the second variable performance control value based on the target power value and the measured power value such that the measured power value converges to the target power value. 
     
     
       11. The storage device of  claim 9 , wherein the first fixed performance control value and the first variable performance control value indicate an input-output bandwidth of the SSD and the second fixed performance control value and the second variable performance control value indicate an operation frequency of the FPGA. 
     
     
       12. The storage device of  claim 9 , wherein in a first priority mode in which the SSD is determined as the priority component and the FPGA is determined as the non-priority component, the global controller enables the first fixed performance controller and the second variable performance controller and disables the second fixed performance controller and the first variable performance controller such that the SSD operates with the fixed performance based on the first fixed performance control value and the FPGA operates with the variable performance based on the second variable performance control value. 
     
     
       13. The storage device of  claim 9 , wherein in a second priority mode in which the FPGA is determined as the priority component and the SSD is determined as the non-priority component, the global controller enables the first variable performance controller and the second fixed performance controller and disables the first fixed performance controller and the second variable performance controller such that the SSD operates with the variable performance based on the first variable performance control value and the FPGA operates with the fixed performance based on the second fixed performance control value. 
     
     
       14. The storage device of  claim 9 , wherein in a non-priority mode in which each of the SSD and the FPGA are determined as the non-priority component, the global controller enables the first variable performance controller and the second variable performance controller and disables the first fixed performance controller and the second fixed performance controller such that the SSD operates with the variable performance based on the first variable performance control value and the FPGA operates with the variable performance based on the second variable performance control value. 
     
     
       15. The storage device of  claim 2 , wherein the global controller receives a ratio of the fixed performance with respect to a maximum performance of the priority component as the target performance value from the host device. 
     
     
       16. The storage device of  claim 2 , wherein:
 each of the SSD and the FPGA includes a temperature sensor configured to generate an operation temperature value indicating an operation temperature of each of the SSD and the FPGA by measuring the operation temperature, and 
 the non-priority component operates with the variable performance based on the target power value, the measured power value, the operation temperature value, and a target temperature value indicating a limit of the operation temperature. 
 
     
     
       17. The storage device of  claim 2 , wherein the power control information is provided based on a command that is transferred from the host device to the SSD. 
     
     
       18. A multi-component device comprising:
 a plurality of components configured to receive power through a power rail connected to a host device; 
 a power sensor connected to the power rail and configured to generate a measured power value corresponding to a total power consumed by the plurality of components by measuring the total power; and 
 a global controller configured to determine one of the plurality of components as a priority component operating with a fixed performance and determine the components except the priority component as non-priority components operating with a variable performance in a priority mode based on power control information provided from the host device. 
 
     
     
       19. The multi-component device of  claim 18 , wherein:
 the global controller monitors whether the total power exceeds a power limit based on a target power value and the measured power value and when the total power exceeds the power limit in the priority mode, the global controller converts from the priority mode to a non-priority mode by determining all of the plurality of components as the non-priority components, and 
 each of the plurality of components operates with the variable performance in the non-priority mode based on the target power value and the measured power value such that the total power does not exceed the power limit. 
 
     
     
       20. A method of controlling an operation of a multi-component device including a plurality of components, the method comprising:
 providing power to the plurality of components through a power rail connected to a host device; 
 generating a measured power value indicating a total power consumed by the plurality of components by measuring the total power using a power sensor connected to the power rail; and 
 determining at least one of the plurality of components as a priority component operating with a fixed performance and determining the components except the priority component as non-priority components operating with a variable performance in a priority mode based on power control information provided from the host device.