Semiconductor device and manufacturing method of 1HE same

Abstract

A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.

What is claimed is: 
     
       1. A manufacturing method of manufacturing a semiconductor device,
 the semiconductor device comprising: 
 a semiconductor substrate; 
 a transistor section provided in the semiconductor substrate to have an emitter region of a first conductivity type on an upper surface side of the semiconductor substrate, and to have a collector region of a second conductivity type in a lower surface side of the semiconductor substrate; 
 a diode section provided in the semiconductor substrate to have a cathode region of the first conductivity type on the lower surface side of the semiconductor substrate; and 
 a boundary section provided between the transistor section and the diode section in the semiconductor substrate to have the collector region in a back surface side of the semiconductor substrate, not having the emitter region on the upper surface side of the semiconductor substrate, 
 wherein the transistor section has one or more gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than the emitter region, and to each of which a gate potential is applied, and 
 an upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section using a mask material such that no lifetime reduction region is provided in any region between the upper surface of the semiconductor substrate and a lower surface of the semiconductor substrate that is overlapped with the one or more gate trench portions in the transistor section in a surface parallel to the upper surface of the semiconductor substrate, and 
 the manufacturing method comprises: 
 forming the upper-surface-side lifetime reduction region by introducing a lifetime killer from the upper surface side of the semiconductor substrate thereinto. 
 
     
     
       2. The manufacturing method according to  claim 1 , comprising:
 the introducing the lifetime killer from the upper surface side of the semiconductor substrate thereinto is performed after formation of an emitter electrode over the upper surface of the semiconductor substrate; and 
 forming a plating layer on an upper surface of the emitter electrode after introducing the lifetime killer. 
 
     
     
       3. The manufacturing method according to  claim 1 , wherein
 the forming the upper-surface-side lifetime reduction region includes: 
 after formation of an emitter electrode over the upper surface of the semiconductor substrate, forming a protective film over the emitter electrode; and 
 introducing the lifetime killer from an upper surface side of the protective film. 
 
     
     
       4. The manufacturing method according to  claim 3 , wherein
 in the forming the protective film, the protective film is formed such that the protective film is not overlapped with the cathode region in a surface parallel to the upper surface of the semiconductor substrate. 
 
     
     
       5. The manufacturing method according to  claim 3 , further comprising:
 forming a mask pattern by a resist to cover the protective film after forming the protective film. 
 
     
     
       6. The manufacturing method according to  claim 3 , wherein the protective film is a continuous layer having a predetermined pattern. 
     
     
       7. The manufacturing method according to  claim 2 , further comprising performing a thermal treatment process, after introducing the lifetime killer and before forming the plating layer. 
     
     
       8. The manufacturing method according to  claim 1 , further comprising:
 forming an emitter electrode over the upper surface of the semiconductor substrate and a collector electrode on the lower surface side of the semiconductor substrate; and 
 forming a plating layer on at least an upper surface of the emitter electrode; 
 wherein 
 the forming the upper-surface-side lifetime reduction region is performed after forming the plating layer, and 
 a thermal treatment process is performed after forming the upper-surface-side lifetime reduction region.