Semiconductor structure with capacitor landing pad and method of making the same

Abstract

A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

What is claimed is: 
     
       1. A fabricating method of a capacitor landing pad, comprising:
 providing a substrate, wherein a plurality of word lines are embedded in the substrate, a plurality of insulating layers are disposed on the word lines, each of the insulating layers is respectively disposed directly on one of the word lines, and an opening is defined between the insulating layers adjacent to each other; 
 forming a metal layer filling in the opening, wherein the insulating layers are entirely embedded in the metal layer; 
 forming a first hard mask covering the metal layer; 
 performing a first pattern process to transform the first hard mask into a plurality of second hard masks by patterning the first hard mask; 
 performing a second pattern process to transform the second hard masks into a plurality of third hard masks by patterning the second hard masks, wherein each of the third hard masks does not connect to another third hard mask, and each of the third hard masks partly overlaps one of the insulating layers; 
 removing the metal layer by taking the third hard masks as a mask to form a trench in the metal layer, wherein the trench extends into the opening, a bottom of the trench is lower than a top surface of the insulating layers, and the trench defines the capacitor landing pad on the metal layer; and 
 forming a dielectric layer filling up the trench. 
 
     
     
       2. The fabricating method of the capacitor landing pad of  claim 1 , further comprising a plurality of bit lines disposed on the substrate, wherein the bit lines intersect the word lines. 
     
     
       3. The fabricating method of the capacitor landing pad of  claim 2 , wherein the trench includes a chessboard pattern, and the trench is parallel to the bit lines. 
     
     
       4. The fabricating method of the capacitor landing pad of  claim 2 , wherein the bottom of the trench is lower than a top surface of each of the bit lines. 
     
     
       5. The fabricating method of the capacitor landing pad of  claim 1 , wherein the first pattern process further comprises:
 forming a first photoresist on the first hard mask before forming the second hard masks; 
 patterning the first photoresist to make the first photoresist comprise a plurality of first rectangular patterns; and 
 transferring the first rectangular patterns to the first hard mask before forming the second hard masks. 
 
     
     
       6. The fabricating method of the capacitor landing pad of  claim 5 , wherein the second pattern process further comprises:
 forming a second photoresist on the second hard masks before forming the third hard masks, wherein the second photoresist comprises a plurality of second rectangular patterns; and 
 transferring the second rectangular patterns to the second hard masks before forming the third hard masks, wherein the second rectangular patterns intersect the first rectangular patterns.