Memory device and method of manufacturing the same

Abstract

Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

What is claimed is: 
     
       1. A memory device, comprising:
 a substrate, having an array region and a staircase region; 
 a stack structure, disposed on the substrate, wherein the stack structure comprises a plurality of dielectric layers and a plurality of conductive layers stacked alternately; 
 a plurality of pads, disposed on the substrate in the staircase region, wherein the plurality of pads are respectively connected to the plurality of conductive layers, so as to form a staircase structure; and 
 a protective layer, disposed on the stack structure to contact a topmost conductive layer, wherein a top surface of the protective layer adjacent to a topmost pad has a curved profile, and the protective layer is only located on the topmost conductive layer. 
 
     
     
       2. The memory device according to  claim 1 , wherein the topmost pad has an extension portion extending to cover a curved top surface of the protective layer. 
     
     
       3. The memory device according to  claim 1 , wherein the protective layer has a thickness greater than a thickness of a topmost dielectric layer. 
     
     
       4. The memory device according to  claim 1 , wherein a ratio of a thickness of the protective layer to a thickness of a topmost dielectric layer is 2:1 to 10:1. 
     
     
       5. The memory device according to  claim 1 , wherein a bottommost conductive layer is a ground select line (GSL), the topmost conductive layer is a string select line (SSL), and the conductive layers between the GSL and the SSL are word lines. 
     
     
       6. The memory device according to  claim 1 , wherein each pad has a thickness greater than or equal to a thickness of each conductive layer. 
     
     
       7. The memory device according to  claim 1 , wherein each pad and a corresponding conductive layer connecting thereto are located at a same level. 
     
     
       8. The memory device according to  claim 1 , further comprising a plurality of vertical channel structures penetrating through the stack structure on the array region, wherein the plurality of vertical channel structures are connected to the substrate in the array region. 
     
     
       9. The memory device according to  claim 8 , wherein each vertical channel structure comprises:
 an epitaxial layer connecting the substrate in the array region; 
 a dielectric pillar disposed on the epitaxial layer; 
 a channel layer encapsulating the dielectric pillar; and 
 a charge storage layer disposed between the channel layer and the stack structure. 
 
     
     
       10. The memory device according to  claim 1 , wherein the substrate further comprises a periphery region, the staircase region is located between the periphery region and the array region, and a plurality of metal-oxide semiconductor (MOS) devices are disposed on the substrate in the periphery region.