Nonvolatile memory device and operation method thereof

Abstract

A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

What is claimed is: 
     
       1. A nonvolatile memory device comprising:
 a nonvolatile memory; 
 a volatile memory configured to operate as a cache memory of the nonvolatile memory and/or a write-back cache; 
 a first controller configured to control the nonvolatile memory and the volatile memory; and 
 a second controller configured to control the nonvolatile memory under a control of the first controller and do not control the volatile memory, the second controller being separate from the first controller, 
 wherein the second controller is configured to perform a flush operation to store in the nonvolatile memory first data that is read from the volatile memory via a dedicated flush channel that provides a data transmission path being a direct path between the volatile memory and the second controller. 
 
     
     
       2. The nonvolatile memory device of  claim 1 , further comprising a buffer configured to temporarily store second data that is read from the nonvolatile memory or third data that is to be stored in the nonvolatile memory. 
     
     
       3. The nonvolatile memory device of  claim 1 , wherein the volatile memory is a DRAM, and the nonvolatile memory is a NAND flash memory. 
     
     
       4. The nonvolatile memory device of  claim 1 , wherein the first controller receives a first command/address and a second command/address from an external device, controls the nonvolatile memory in response to the first command/address, and controls the volatile memory in response to the second command/address. 
     
     
       5. The nonvolatile memory device of  claim 1 , wherein the first controller is a register clock driver (RCD). 
     
     
       6. The nonvolatile memory device of  claim 1 , wherein the volatile memory and the second controller share a memory data line. 
     
     
       7. The nonvolatile memory device of  claim 1 , wherein the volatile memory and the first controller share a tag data line. 
     
     
       8. The nonvolatile memory device of  claim 1 , wherein the volatile memory, the first controller and the second controller share a tag data line. 
     
     
       9. The nonvolatile memory device of  claim 1 , wherein the first controller determines whether a cache miss or a cache hit occurs. 
     
     
       10. The nonvolatile memory device of  claim 9 , wherein when the cache miss occurs during a write operation, the second controller performs the flush operation, and
 wherein when the cache hit occurs, the second controller does not perform the flush operation. 
 
     
     
       11. The nonvolatile memory device of  claim 9 , wherein the first controller determines whether the cache hit or the cache miss occurs, based on a result of comparing a command/address from an external device and a tag from the volatile memory. 
     
     
       12. The nonvolatile memory device of  claim 11 , wherein the cache hit indicates a case that data corresponding to the command/address is stored in the volatile memory, and
 wherein the cache miss indicates a case that no data corresponding to the command/address is stored in the volatile memory. 
 
     
     
       13. A nonvolatile memory device comprising:
 a nonvolatile memory; 
 a volatile memory configured to operate as a cache memory of the nonvolatile memory and/or a write-back cache; 
 a first controller configured to control the nonvolatile memory and the volatile memory; and 
 a second controller configured to control the nonvolatile memory under a control of the first controller and do not control the volatile memory, the second controller being separate from the first controller, 
 wherein the second controller is configured to selectively perform a flush operation or a read caching operation, 
 wherein the flush operation is an operation of programming first data of the volatile memory in the nonvolatile memory via a dedicated flush path that provides a data transmission path being a direct path between the volatile memory and the second controller, and 
 wherein the read caching operation is an operation of writing second data of the nonvolatile memory in the volatile memory. 
 
     
     
       14. The nonvolatile memory device of  claim 13 , wherein the second controller is configured to selectively perform the flush operation or the read caching operation based on a tag received from the volatile memory. 
     
     
       15. The nonvolatile memory device of  claim 13 , wherein the first controller determines whether a cache miss or a cache hit occurs based on a tag received from the volatile memory,
 wherein when the cache miss occurs during a write operation, the second controller performs the flush operation, 
 wherein when the cache hit occurs, the second controller does not perform the flush operation, 
 wherein the cache hit indicates a case that data corresponding to a command/address received from an external device is stored in the volatile memory, and 
 wherein the cache miss indicates a case that no data corresponding to the command/address is stored in the volatile memory. 
 
     
     
       16. The nonvolatile memory device of  claim 13 , wherein the second controller includes a flush manager configured to control the flush operation on the first data received from the volatile memory. 
     
     
       17. A heterogeneous memory device comprising:
 a nonvolatile memory; 
 a volatile memory configured to operate under a control of an external controller; and 
 a controller configured to control the nonvolatile memory under the control of the external controller and not the volatile memory, 
 wherein the controller is configured to selectively perform a flush operation and/or a read caching operation, 
 wherein the flush operation is an operation of programming first data of the volatile memory in the nonvolatile memory via a dedicated flush channel that provides a data transmission path being a direct path between the volatile memory and the controller, and 
 wherein the read caching operation is an operation of writing second data of the nonvolatile memory in the volatile memory. 
 
     
     
       18. The heterogeneous memory device of  claim 17 , wherein the volatile memory and the controller share a memory data line and a tag data line. 
     
     
       19. The heterogeneous memory device of  claim 17 , wherein when a cache miss occurs during a write operation, the controller performs the flush operation,
 wherein when a cache hit occurs, the controller does not perform the flush operation, 
 wherein the cache hit indicates a case that data corresponding to a command/address is stored in the volatile memory, and 
 wherein the cache miss indicates a case that no data corresponding to the command/address is stored in the volatile memory. 
 
     
     
       20. The heterogeneous memory device of  claim 17 , wherein the controller is configured to selectively perform the flush operation or the read caching operation based on a tag received from the volatile memory.