US11617264B2ActiveUtilityA1

Interconnect substrate and method of making the same

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Assignee: SHINKO ELECTRIC IND COPriority: Sep 28, 2020Filed: Sep 17, 2021Granted: Mar 28, 2023
Est. expirySep 28, 2040(~14.2 yrs left)· nominal 20-yr term from priority
Inventors:Yuji Yukiiri
H05K 1/0313H05K 3/4673H05K 2201/0209H05K 2201/0269H05K 1/0353H05K 1/11H05K 2203/122H05K 1/115
58
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Cited by
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References
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Claims

Abstract

An interconnect substrate includes a first insulating layer, an interconnect layer formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer to cover the interconnect layer, wherein the second insulating layer includes a first resin layer and a second resin layer, the first resin layer covering at least part of a surface of the interconnect layer exposed outside the first insulating layer, the second resin layer covering the first resin layer, wherein both the first resin layer and the second resin layer contain a resin and a filler, and wherein a proportion of the resin in the first resin layer per unit area is higher than a proportion of the resin in the second resin layer per unit area.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An interconnect substrate, comprising:
 a first insulating layer; and 
 an interconnect layer formed on a first surface of the first insulating layer; and 
 a second insulating layer formed on the first surface of the first insulating layer to cover the interconnect layer, 
 wherein the second insulating layer includes a first resin layer and a second resin layer, the first resin layer covering at least part of a surface of the interconnect layer exposed outside the first insulating layer, the second resin layer covering the first resin layer, 
 wherein the second resin layer is in contact with both the first resin layer and the first surface of the first insulating layer, 
 wherein both the first resin layer and the second resin layer contain a resin and a filler, and 
 wherein a proportion of the resin in the first resin layer per unit area is higher than a proportion of the resin in the second resin layer per unit area. 
 
     
     
       2. The interconnect substrate as claimed in  claim 1 , wherein the proportion of the resin in the first resin layer per unit area is greater than or equal to 1.5 times the proportion of the resin in the second resin layer per unit area. 
     
     
       3. The interconnect substrate as claimed in  claim 1 , wherein a proportion of the filler in the first resin layer per unit area is lower than a proportion of the filler in the second resin layer per unit area. 
     
     
       4. The interconnect substrate as claimed in  claim 1 , wherein a thickness of the first resin layer is less than a thickness of the second resin layer. 
     
     
       5. The interconnect substrate as claimed in  claim 1 , wherein a content of the filler in the second resin layer as a whole is greater than or equal to 50 wt %. 
     
     
       6. The interconnect substrate as claimed in  claim 1 , wherein a surface roughness of the surface of the interconnect layer exposed outside the first insulating layer is less than or equal to 200 nm. 
     
     
       7. The interconnect substrate as claimed in  claim 1 , further comprising a via interconnect embedded in the second insulating layer and extending through the first resin layer and the second resin layer to come in contact with the interconnect layer. 
     
     
       8. The interconnect substrate as claimed in  claim 1 , wherein a thickness of the first resin layer is less than a thickness of the interconnect layer. 
     
     
       9. The interconnect substrate as claimed in  claim 1 , wherein the first resin layer and the second resin layer are made of a thermosetting resin. 
     
     
       10. The interconnect substrate as claimed in  claim 1 , wherein the interconnect layer has a first surface facing the first insulating layer, a second surface opposite the first surface of the interconnect layer, and a side surface,
 wherein the second surface of the interconnect layer and the side surface of the interconnect layer are exposed outside the first insulating layer, and 
 wherein the first resin layer covers the second surface of the interconnect layer and the side surface of the interconnect layer.

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