Semiconductor structure and forming method thereof

Abstract

Disclosed are a semiconductor structure and a forming method thereof. In one form, a forming method includes: providing a base, including a substrate and a plurality of fins protruding from the substrate, an interlayer dielectric layer formed on the substrate, a gate opening formed in the interlayer dielectric layer, the gate opening spanning the fin and exposing a part of a top and a part of a sidewall of the fin, and a source/drain doped region formed in the fins on two sides of the gate opening, where the substrate includes a first region and a second region adjacent to each other, to respectively form transistors, the gate opening located in either of the first region and the second region extends to the other region and exposes the fin of the other region, and a position of the exposed fin of the other region is used as an interconnect position; forming a gate dielectric layer covering a bottom and a sidewall of the gate opening and the fin in the gate opening conformally; removing the gate dielectric layer on a surface of the fin at the interconnect position, to expose the surface of the fin at the interconnect position; and forming a gate structure in the gate opening after the surface of the fin at the interconnect position is exposed. The present disclosure enlarges a process window for electrical connection.

What is claimed is: 
     
       1. A semiconductor structure, comprising:
 a base, comprising a substrate and a plurality of fins protruding from the substrate, wherein the substrate comprises, along an arrangement direction of the plurality of fins, a first region and a second region adjacent to each other, where the first region and the second region are configured for use in for forming transistors; 
 a gate structure, spanning the plurality of fins and covering a part of a top and a part of a sidewall of the fins of the plurality of fins, wherein the gate structure located in the first region extends to the second region and covers a middle portion of the fin of the second region, where a position of the covered fin of the second region is used as an interconnect position, and the gate structure and the fin are directly electrically connected at the interconnect position; 
 a source doped region and a drain doped region, located in the fins of the plurality of fins on two sides of the gate structure, where the interconnect position is located between the source doped region and the drain doped region in the fin of the second region and the gate structure is electrically connected to the source doped region and the drain doped region in the fin corresponding to the interconnect position; 
 a gate dielectric layer, located between the gate structure and the base, the gate dielectric layer exposing a surface of the fin at the interconnect position; and 
 an interlayer dielectric layer, located on the substrate on a side of the gate structure and covering a sidewall of the gate structure. 
 
     
     
       2. The semiconductor structure according to  claim 1 , further comprising:
 a cap layer, located between the gate structure and the gate dielectric layer, and exposing the surface of the fin at the interconnect position. 
 
     
     
       3. The semiconductor structure according to  claim 1 , wherein:
 the semiconductor structure further comprises a metal silicide layer covering the surface of the fin at the interconnect position; or 
 a material of the fin at the interconnect position comprises a metal silicide material that is used as a metal silicide layer. 
 
     
     
       4. The semiconductor structure according to  claim 3 , wherein the metal silicide layer is in contact with an adjacent source/drain doped region in the fin corresponding to the interconnect position. 
     
     
       5. The semiconductor structure according to  claim 1 , wherein:
 the semiconductor structure comprises a SRAM device, and the first region and the second region are configured respectively for use in forming a first pull-up transistor and a second pull-up transistor; 
 the gate structure in the first region extends to the second region and covers the fins of the plurality of fins in the second region, and in the second region, a position of the fins of the plurality of fins covered by the gate structure in the first region is used as the interconnect position; and 
 the gate structure in the second region extends to the first region and covers the fins of the plurality of fins in the first region, and in the first region, a position of the fins of the plurality of fins covered by the gate structure in the second region is used as the interconnect position. 
 
     
     
       6. The semiconductor structure according to  claim 1 , wherein the gate structure comprises a metal gate structure. 
     
     
       7. A forming method of a semiconductor structure, comprising:
 providing a base, comprising:
 a substrate and a plurality of fins protruding from the substrate, 
 an interlayer dielectric layer formed on the substrate, 
 
 a gate opening formed in the interlayer dielectric layer, the gate opening spanning the plurality of fins and exposing a part of a top and a part of a sidewall of the fins of the plurality of fins, and 
 a source doped region and a drain doped region formed in the fins of the plurality of fins on two sides of the gate opening, 
 wherein the substrate comprises, along an arrangement direction of the plurality of fins, a first region and a second region adjacent to each other, where the first region and the second region are respectively used for forming transistors, the gate opening located in the first region extends to the second region and exposes a middle portion of the fin of the second region, and where a position of the exposed fin of the second region is used as an interconnect position, the interconnect position is located between the source doped region and the drain doped region; 
 forming a gate dielectric layer covering a bottom and a sidewall of the gate opening and the fin in the gate opening conformally; 
 removing the gate dielectric layer on a surface of the fin at the interconnect position, to expose the surface of the fin at the interconnect position; and 
 forming a gate structure in the gate opening after the surface of the fin at the interconnect position is exposed. 
 
     
     
       8. The forming method of a semiconductor structure according to  claim 7 , wherein:
 after forming a gate dielectric layer on a bottom and a sidewall of the gate opening, and before removing the gate dielectric layer on a surface of the fin at the interconnect position, the forming method further comprises:
 forming a planarization layer in the gate opening; 
 
 patterning the planarization layer, and forming an opening in the planarization layer at the interconnect position; and 
 removing, along the opening, the gate dielectric layer on the surface of the fin at the interconnect position; and 
 after removing the gate dielectric layer on the surface of the fin at the interconnect position, the forming method further comprises: removing the planarization layer. 
 
     
     
       9. The forming method of a semiconductor structure according to  claim 7 , wherein:
 after forming a gate dielectric layer on a bottom and a sidewall of the gate opening, and before removing the gate dielectric layer on a surface of the fin at the interconnect position, the forming method further comprises: forming a cap layer covering the gate dielectric layer conformally; and 
 before removing a gate dielectric layer on a surface of the fin at the interconnect position, the forming method further comprises: removing the cap layer on the surface of the fin at the interconnect position. 
 
     
     
       10. The forming method of a semiconductor structure according to  claim 9 , wherein the cap layer on the surface of the fin at the interconnect position is removed by using a dry etching process. 
     
     
       11. The forming method of a semiconductor structure according to  claim 7 , wherein after removing the gate dielectric layer on a surface of the fin at the interconnect position, to expose the surface of the fin at the interconnect position, and before forming a gate structure in the gate opening, the forming method further comprises: performing metal silicide processing on the surface of the fin exposed at the interconnect position, to form a metal silicide layer. 
     
     
       12. The forming method of a semiconductor structure according to  claim 11 , wherein in the step of forming the metal silicide layer, the metal silicide layer is in contact with the adjacent source/drain doped region in the fin corresponding to the interconnect position. 
     
     
       13. The forming method of a semiconductor structure according to  claim 7 , wherein
 before the forming an interlayer dielectric layer, the forming method further comprises: 
 forming a dummy gate layer on the base, the dummy gate layer spanning the fin and covering a part of a top and a part of a sidewall of the fin; and 
 forming the interlayer dielectric layer on the base on a side of the dummy gate layer, the interlayer dielectric layer exposing a top of the dummy gate layer; and 
 the step of forming the gate opening comprises: removing the dummy gate layer. 
 
     
     
       14. The forming method of a semiconductor structure according to  claim 7 , wherein the gate dielectric layer on the surface of the fin at the interconnect position is removed using a dry etching process, to expose the surface of the fin at the interconnect position. 
     
     
       15. The forming method of a semiconductor structure according to  claim 7 , wherein:
 the semiconductor structure is a SRAM device, and the first region and the second region are respectively used for forming a first pull-up transistor and a second pull-up transistor; 
 the gate opening in the first region extends to the second region and exposes the fin in the second region, and in the second region, a position of the fin exposed by the gate opening in the first region is used as the interconnect position; and 
 the gate opening in the second region extends to the first region and exposes the fin in the first region, and in the first region, a position of the fin exposed by the gate opening in the second region is used as the interconnect position. 
 
     
     
       16. The forming method of a semiconductor structure according to  claim 7 , wherein the gate structure comprises a metal gate structure.