Contact pad structures and methods for fabricating contact pad structures

Abstract

A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects.

The invention claimed is: 
     
       1. A semiconductor structure comprising:
 a conductive pad comprising an electrically conductive material; 
 a slot arranged through the conductive pad and comprising an electrically insulating material; 
 a passivation layer arranged over the conductive pad and comprising an opening that exposes a portion of the conductive pad; and 
 a plurality of electrical interconnects arranged under the conductive pad; 
 wherein the slot is arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects, 
 wherein the passivation layer covers the slot. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein the slot is arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects along a first direction; and
 wherein the slot comprises an elongate slot extending longitudinally along a second direction substantially perpendicular to the first direction. 
 
     
     
       3. The semiconductor structure of  claim 1 , wherein the plurality of electrical interconnects is a first plurality of electrical interconnects;
 wherein the semiconductor structure further comprises a second plurality of electrical interconnects arranged under the conductive pad; and 
 wherein the second plurality of electrical interconnects is arranged laterally between the exposed portion of the conductive pad and the slot. 
 
     
     
       4. The semiconductor structure of  claim 3 , further comprising an electrically conductive element arranged under the second plurality of electrical interconnects. 
     
     
       5. The semiconductor structure of  claim 3 , wherein the passivation layer is arranged over the second plurality of electrical interconnects. 
     
     
       6. The semiconductor structure of  claim 1 , wherein the slot is a first slot;
 wherein the semiconductor structure further comprises a second slot arranged through the conductive pad and comprising an electrically insulating material; and 
 wherein the first slot is arranged laterally between the second slot and the plurality of electrical interconnects. 
 
     
     
       7. The semiconductor structure of  claim 6 , wherein a length of the second slot is less than a length of the first slot. 
     
     
       8. The semiconductor structure of  claim 6 , wherein the passivation layer extends continuously over the first slot and the plurality of electrical interconnects, wherein the passivation layer is arranged over the second slot. 
     
     
       9. The semiconductor structure of  claim 6 , wherein the plurality of electrical interconnects is a first plurality of electrical interconnects;
 wherein the semiconductor structure further comprises a second plurality of electrical interconnects; and 
 wherein the second plurality of electrical interconnects is arranged laterally between the exposed portion of the conductive pad and the second slot. 
 
     
     
       10. The semiconductor structure of  claim 6 , further comprising a third slot arranged through the conductive pad and comprising an electrically insulating material; and
 wherein the first slot is further arranged laterally between the third slot and the plurality of electrical interconnects. 
 
     
     
       11. The semiconductor structure of  claim 10 , wherein the first slot is arranged laterally between the third slot and the plurality of electrical interconnects along a first direction, and wherein the second slot and the third slot are substantially horizontally aligned along a second direction substantially perpendicular to the first direction. 
     
     
       12. The semiconductor structure of  claim 10 , wherein a length of the second slot is approximately equal to a length of the third slot. 
     
     
       13. The semiconductor structure of  claim 10 , wherein the plurality of electrical interconnects is a first plurality of electrical interconnects;
 wherein the semiconductor structure further comprises a second plurality of electrical interconnects arranged under the conductive pad; and 
 wherein the second plurality of electrical interconnects is arranged laterally between the exposed portion of the conductive pad and the second slot, and is further arranged laterally between the exposed portion of the conductive pad and the third slot. 
 
     
     
       14. The semiconductor structure of  claim 9 , wherein the semiconductor structure further comprises a third plurality of electrical interconnects, and a third slot and a fourth slot arranged through the conductive pad and comprising an electrically insulating material;
 wherein the third slot is arranged laterally between the fourth slot and the third plurality of electrical interconnects; and 
 wherein the second plurality of electrical interconnects is arranged laterally between the exposed portion of the conductive pad and the fourth slot. 
 
     
     
       15. The semiconductor structure of  claim 14 , wherein the third slot is arranged laterally between the fourth slot and the third plurality of electrical interconnects along a first direction;
 wherein the first slot is substantially horizontally aligned with the third slot along a second direction substantially perpendicular to the first direction; and 
 wherein the second slot is substantially horizontally aligned with the fourth slot along the second direction. 
 
     
     
       16. The semiconductor structure of  claim 14 , further comprising an electrically conductive element arranged under the second plurality of electrical interconnects, wherein the electrically conductive element extends partially across a length of the second slot and partially across a length of the fourth slot. 
     
     
       17. The semiconductor structure of  claim 1 , wherein the electrically insulating material comprises an oxide, and wherein the electrically conductive material comprises copper. 
     
     
       18. The semiconductor structure of  claim 1 , wherein the slot is arranged fully through the conductive pad. 
     
     
       19. The semiconductor structure of  claim 1 , wherein the slot is arranged directly below the passivation layer and the plurality of electrical interconnects is arranged directly under the conductive pad. 
     
     
       20. A method for fabricating a semiconductor structure, wherein the method comprises:
 forming a conductive pad comprising an electrically conductive material; 
 forming a slot comprising an electrically insulating material through the conductive pad; 
 forming a passivation layer over the conductive pad, wherein the passivation layer comprises an opening that exposes a portion of the conductive pad; and 
 forming a plurality of electrical interconnects under the conductive pad; 
 wherein the slot is arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects, 
 wherein the passivation layer covers the slot.