In-memory computation device and in-memory computation method to perform multiplication operation in memory cell array according to bit orders

Abstract

An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

What is claimed is: 
     
       1. An in-memory computation device, comprising:
 a memory cell array, comprising: 
 a memory cell block, corresponding to at least one word line, wherein the memory cell block is configured to store a plurality of weight values, and a plurality of memory cells on the memory cell block store a plurality of corresponding bits of each of the weight values; and 
 an input buffer, coupled to a plurality of bit lines, and respectively transmitting a plurality of input signals to the plurality of bit lines, 
 wherein a plurality of memory cells of the memory cell array perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and
 a sense amplifier, performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders corresponding to the plurality of first operation results. 
 
 
     
     
       2. The in-memory computation device according to  claim 1 , wherein the input buffer enables a plurality of bits of each of the input signals to be transmitted to a plurality of corresponding bit lines in a time-sharing manner. 
     
     
       3. The in-memory computation device according to  claim 2 , wherein a number of the plurality of corresponding bit lines is equal to a bit number of each of the weight values. 
     
     
       4. The in-memory computation device according to  claim 2 , wherein the sense amplifier comprises:
 a plurality of sensing circuits, respectively coupled to the plurality of corresponding bit lines, and configured to sense current states on the plurality of corresponding bit lines, so as to determine the plurality of first operation results; 
 a plurality of first multipliers, enabling the plurality of first operation results to be multiplied by 2 to an N-th power, so as to generate a plurality of first signals, where N is determined according to the plurality of bit orders respectively corresponding to the plurality of first operation results, and N is an integer greater than or equal to 0; 
 a second multiplier, coupled to the plurality of first multipliers, and enabling the plurality of first signals to be multiplied by 2 to a y-th power, so as to generate a plurality of second signals, where y is determined according to a time sequence of transmission of each of the bits of each of the input signals, and y is an integer greater than or equal to 0; and 
 an adder, coupled to the second multiplier, adding the plurality of second signals to generate the second operation result. 
 
     
     
       5. The in-memory computation device according to  claim 1 , wherein the input buffer enables a plurality of bits of each of the input signals to be transmitted to a plurality of corresponding bit lines in parallel, and a number of the plurality of corresponding bit lines is equal to multiplication of a bit number of each of the weight values and a bit number of each of the input signals. 
     
     
       6. The in-memory computation device according to  claim 5 , wherein the plurality of bits of the plurality of weight values are duplicated to become a plurality of duplicated weight values, and the memory cell block is on the plurality of corresponding bit lines and respectively stores a plurality of bits of the plurality of duplicated weight values. 
     
     
       7. The in-memory computation device according to  claim 5 , wherein the sense amplifier comprises:
 a plurality of sensing circuits, respectively coupled to the plurality of corresponding bit lines, and configured to sense current states on the plurality of corresponding bit lines, so as to determine the plurality of first operation results; 
 a plurality of multipliers, enabling the plurality of first operation results to be multiplied by 2 to an N-th power, so as to generate a plurality of first signals, where N is determined according to the plurality of bit orders respectively corresponding to the plurality of first operation results; and 
 an adder, coupled to the first multiplier, and adding the plurality of first signals to generate the second operation result. 
 
     
     
       8. The in-memory computation device according to  claim 5 , wherein the plurality of corresponding bit lines in a same bit order corresponding to each of the input signals are adjacently arranged. 
     
     
       9. The in-memory computation device according to  claim 5 , wherein the plurality of corresponding bit lines are sequentially arranged according to a bit order of the plurality of bits of each of the corresponding input signal. 
     
     
       10. The in-memory computation device according to  claim 5 , wherein the plurality of bits of each of the input signal generate an input arrangement sequence according to a bit order of the correspondingly generated plurality of first operation results, and the input buffer respectively transmits the plurality of bits of each of the input signals to the plurality of corresponding bit lines according to the input arrangement sequence. 
     
     
       11. The in-memory computation device according to  claim 5 , wherein the memory cell block comprises a plurality of memory columns, and the at least one word line is a plurality of word lines and respectively corresponds to the memory columns, each of the memory columns stores at least one of the plurality of bits of the plurality of weight values in a field corresponding to each of the input signals. 
     
     
       12. The in-memory computation device according to  claim 11 , wherein the sense amplifier comprises:
 a plurality of sensing and amplifying circuits, respectively coupled to the plurality of corresponding bit lines, and configured to sense current states on the plurality of corresponding bit lines, so as to determine the plurality of first operation results; 
 a multiplier, enabling the plurality of first operation results to be multiplied by 2 to an N-th power, so as to generate a plurality of first signals, where N is determined according to an order of switched-on bit lines in the plurality of word lines, and N is an integer greater than or equal to 0; and 
 an adder, coupled to the multiplier, and adding the plurality of first signals to generate the second operation result. 
 
     
     
       13. The in-memory computation device according to  claim 1 , wherein the memory cell array is a reverse flash memory cell array.