Tile-based result buffering in memory-compute systems

Abstract

A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. A first tile in a first node can include a processor with a processor output and a first register network configured to receive information from the processor output and information from one or more of the multiple other tiles in the first node. In response to an output instruction and a delay instruction, the register network can provide an output signal to one of the multiple other tiles in the first node. Based on the output instruction, the output signal can include one or the other of the information from the processor output and the information from one or more of the multiple other tiles in the first node. A timing characteristic of the output signal can depend on the delay instruction.

What is claimed is: 
     
       1. A system comprising:
 multiple memory-compute nodes coupled in a reconfigurable compute fabric, wherein each of the nodes comprises a hybrid threading processor and a hybrid threading fabric, and wherein the hybrid threading fabric of each node comprises multiple tiles; and 
 a first memory-compute tile of a first node of the multiple memory-compute nodes, the first memory-compute tile coupled to multiple other tiles in the first node, wherein each of the tiles in the first node includes respective processing and storage elements, and wherein the first memory-compute tile comprises:
 a first processor with a processor output; and 
 a first register network configured to:
 receive information comprising a first compute result from the processor output and information from one or more of the multiple other tiles in the first node; 
 store the first compute result in a specified output register and in a specified delay register; and 
 provide an output signal to one of the multiple other tiles in the first node; 
 
 
 wherein the output signal includes one or the other of the information from the processor output and the information from one or more of the multiple other tiles in the first node; and 
 wherein a timing characteristic of the output signal depends on a delay indication. 
 
     
     
       2. The system of  claim 1 , wherein the first processor includes a multiply/shift processor and an arithmetic/logic processor. 
     
     
       3. The system of  claim 2 , wherein:
 the multiply/shift processor includes first and second multiply/shift inputs and a multiply/shift output; 
 the arithmetic/logic processor includes first and second arithmetic/logic inputs and an arithmetic/logic output; and 
 the multiply/shift output is coupled to the first arithmetic/logic input. 
 
     
     
       4. The system of  claim 1 , wherein the first register network comprises:
 N delay registers respectively corresponding to the multiple other tiles in the first node to which the first memory-compute tile is coupled; and 
 N output registers respectively corresponding to each of the delay registers. 
 
     
     
       5. The system of  claim 4 , further comprising:
 a pass-through delay register comprising a first input coupled to the processor output and a first feedback input coupled to an output of the pass-through delay register; and 
 a pass-through output register comprising a second input coupled to the processor output, a third input coupled to the output of the pass-through delay register, and a second feedback input coupled to an output of the pass-through output register. 
 
     
     
       6. The system of  claim 5 , further comprising a register controller configured to provide flow control signals to each of the N delay registers, the N output registers, the pass-through delay register, and the pass-through output register. 
     
     
       7. The system of  claim 4 , wherein a first delay register of the N delay registers is configured to provide, to a corresponding first output register of the N output registers, information from the processor output from a current time slice or from a previous time slice; and
 wherein a second delay register of the N delay registers is configured to provide, to a corresponding second output register of the N output registers, one of (1) the information from the one or more of the multiple other tiles, (2) the information from the processor output from a current time slice, or (3) the information from the processor output from the previous time slice. 
 
     
     
       8. The system of  claim 7 , wherein a time slice comprises a fraction of a clock cycle. 
     
     
       9. The system of  claim 4 , wherein a first delay register of the N delay registers includes respective inputs coupled to the processor output and to an output of the first delay register; and
 wherein a second delay register of the N delay registers includes respective inputs coupled to the processor output, to an output of the second delay register, and to one or more of the multiple other tiles in the first node. 
 
     
     
       10. The system of  claim 9 , wherein the inputs of the first delay register are decoupled from outputs of the other tiles in the first node. 
     
     
       11. A method comprising:
 at a first register network in a first memory-compute tile:
 receiving first information comprising a first compute result; 
 providing the first information to a first delay register and to a first output register; 
 maintaining the first information at the first delay register; 
 receiving second information comprising a second compute result, the second compute result occurring after the first compute result; 
 providing the second information to the first delay register and to the first output register; and 
 
 using the first output register, providing the second information to a second memory-compute tile and subsequently providing the first information to the same second memory-compute tile; 
 wherein the first and second memory-compute tiles comprise a reconfigurable compute fabric. 
 
     
     
       12. The method of  claim 11 , wherein receiving the first information includes receiving information from a processor on the first memory-compute tile. 
     
     
       13. The method of  claim 12 , wherein receiving the second information includes receiving information from the processor on the first memory-compute tile. 
     
     
       14. The method of  claim 12 , wherein receiving the second information includes receiving information from a different processor on a different memory-compute tile of the reconfigurable compute fabric. 
     
     
       15. The method of  claim 11 , wherein providing the second information to the second memory-compute tile corresponds to a first time slice, wherein providing the first information to the same second memory-compute tile corresponds to a second time slice following the first time slice, and wherein a time slice comprises a portion of a clock cycle. 
     
     
       16. The method of  claim 11 , wherein maintaining the first information at the first delay register comprises receiving output information from the first delay register, at an input of the first delay register, over one or more time slices. 
     
     
       17. The method of  claim 11 , further comprising, at the first register network in the first memory-compute tile:
 at a first time slice, providing third information comprising a third compute result to a second output register; 
 at a subsequent time slice, receiving the third information at an input buffer of the first memory-compute tile, the input buffer coupled to an output of the second output register. 
 
     
     
       18. The method of  claim 11 , further comprising using a controller for a synchronous flow, generating respective register control signals to control the first delay register and the first output register. 
     
     
       19. A non-transitory machine-readable medium comprising instructions thereon that, when executed by a computer architecture, causes the computer architecture to execute operations comprising:
 at a first register network in a first memory-compute tile:
 determining a first compute result and subsequently determining a second compute result; 
 providing the first compute result to a first delay register and to a first output register; 
 maintaining the first compute result at the first delay register; 
 providing the second compute result to the first delay register and to the first output register; and 
 using the first output register and corresponding to a first time slice, providing the second compute result to a first destination; 
 
 providing the first compute result from the first delay register to the first output register; and 
 using the first output register and corresponding to a subsequent time slice, providing the first compute result to the first destination. 
 
     
     
       20. The non-transitory machine-readable medium of  claim 19 , the operations further comprising:
 providing the second compute result to an input of a different second memory-compute tile.