Interface clock management

Abstract

The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

What is claimed is: 
     
       1. A memory device, comprising:
 an interface to receive a first command, timed by a clock signal, that specifies a read of a status register; 
 a first receiver circuit to receive the clock signal; 
 a first driver circuit to serially transmit information from the status register to an external device; and 
 a second driver circuit to drive a resume signal that indicates whether the memory device is ready to receive the clock signal. 
 
     
     
       2. The memory device of  claim 1 , wherein the clock signal is deactivated based at least in part on the resume signal. 
     
     
       3. The memory device of  claim 1 , wherein the first command comprises a plurality of bits that are received synchronously with respect to the clock signal. 
     
     
       4. The memory device of  claim 1 , wherein the second driver circuit is configured for wired-OR operation of the resume signal with at least one additional memory device. 
     
     
       5. The memory device of  claim 1 , wherein the interface is to receive a second command that specifies a read of a memory array. 
     
     
       6. The memory device of  claim 5 , further comprising:
 a plurality of drivers to transmit data from the read of the memory array. 
 
     
     
       7. The memory device of  claim 6 , wherein the plurality of drivers transmit the data from the read of the memory array synchronously with respect to the clock signal. 
     
     
       8. A memory device, comprising:
 a status register; 
 an interface to receive a first command that indicates a read of the status register; 
 a first driver circuit to, in response to at least the first command, serially transmit information from the status register to an external device; and 
 a second driver circuit to drive a resume signal that indicates whether the memory device is ready to receive a clock signal that synchronizes the first driver circuit. 
 
     
     
       9. The memory device of  claim 8 , wherein the interface is to receive a second command that indicates a read of memory array data. 
     
     
       10. The memory device of  claim 9 , further comprising:
 a plurality of drivers to transmit the memory array data. 
 
     
     
       11. The memory device of  claim 10 , wherein the plurality of drivers transmit the memory array data synchronously with respect to the clock signal. 
     
     
       12. The memory device of  claim 11 , wherein the clock signal is to be deactivated by an external device based at least in part on the resume signal. 
     
     
       13. The memory device of  claim 12 , wherein the first command comprises a plurality of bits that are received synchronously with respect to the clock signal. 
     
     
       14. The memory device of  claim 13 , wherein the second driver circuit is configured for wired-OR operation of the resume signal with at least one additional memory device. 
     
     
       15. A method of operating a memory device, comprising:
 receiving, by an interface and timed by a selectively activated clock signal, a first command, the first command indicating a read of a status register; 
 receiving, by first receiver circuit, the selectively activated clock signal; 
 serially transmitting, based at least in part on the first command, by a first driver circuit, and to an external device, information from the status register; and 
 transmitting, by a second driver circuit, a resume signal that indicates whether the memory device is ready to receive the selectively activated clock signal. 
 
     
     
       16. The method of  claim 15 , wherein the selectively activated clock signal is deactivated based at least in part on the resume signal. 
     
     
       17. The method of  claim 16 , wherein the first command comprises a plurality of bits that are received synchronously with respect to the selectively activated clock signal. 
     
     
       18. The method of  claim 17 , wherein the second driver circuit is configured for wired-OR operation of the resume signal with at least one additional memory device. 
     
     
       19. The method of  claim 18 , wherein the interface is to receive a second command that specifies a read of memory array data. 
     
     
       20. The method of  claim 19 , further comprising:
 transmitting, using a plurality of drivers and timed by the selectively activated clock signal, the memory array data.