Semiconductor device including an active component and a barrier pattern surrounding the active component and method of forming the same

Abstract

Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 active components disposed on a substrate, wherein each of the active components comprises:
 base insulation patterns disposed on the substrate, extending in a first direction, and spaced apart from each other in a second direction different from the first direction; 
 gate electrodes disposed on the substrate, extending in the first direction, and spaced apart from each other with the base insulation patterns interposed therebetween; 
 a gate dielectric layer disposed on the gate electrodes and the base insulation patterns; 
 a channel pattern disposed on the gate dielectric layer; 
 source electrodes disposed on the channel pattern and spaced apart from each other; 
 a drain electrode disposed on the channel pattern and between the source electrodes; and 
 second insulation patterns disposed on the channel pattern and between the source electrodes and the drain electrode; and 
 
 a first barrier pattern disposed on the gate dielectric layer and surrounding the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns in each of the active components. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the second insulation patterns in each of the active components are spaced apart from each other. 
     
     
       3. The semiconductor device of  claim 1 , wherein the first barrier pattern comprises an insulating material having a different etch selectivity from the second insulation patterns. 
     
     
       4. The semiconductor device of  claim 1 , wherein the channel pattern comprises first sidewalls opposite to each other and extending in the first direction and second sidewalls opposite to each other and extending in the second direction, and
 the first sidewalls of the channel pattern are substantially coplanar with sidewalls of the source electrodes that are in contact with the first barrier pattern and extend in the first direction. 
 
     
     
       5. The semiconductor device of  claim 4 , wherein the second sidewalls of the channel pattern are substantially coplanar with sidewalls of the source electrodes that are in contact with the first barrier pattern and extend in the second direction. 
     
     
       6. The semiconductor device of  claim 4 , wherein the second sidewalls of the channel pattern are substantially coplanar with sidewalls of the drain electrode that are in contact with the first barrier pattern. 
     
     
       7. The semiconductor device of  claim 4 , wherein the second sidewalls of the channel pattern are substantially coplanar with sidewalls of the second insulation patterns that are in contact with the first barrier pattern. 
     
     
       8. The semiconductor device of  claim 1 , wherein the drain electrode comprises a first portion overlapping one of the gate electrodes in a third direction perpendicular to the first direction and the second direction, a second portion overlapping another one of the gate electrodes in the third direction, and a third portion between the first portion and the second portion and overlapping the channel pattern in the third direction. 
     
     
       9. The semiconductor device of  claim 1 , wherein each of the active components comprise second barrier patterns between the second insulation patterns and the channel pattern and between the source electrodes and the drain electrode. 
     
     
       10. The semiconductor device of  claim 1 , wherein each of the active components comprise conductive patterns between the source electrodes and the channel pattern and between the drain electrode and the channel pattern. 
     
     
       11. A semiconductor device, comprising:
 active components spaced apart from each other on a substrate, wherein each of the active components comprises:
 a gate electrode disposed on the substrate; 
 a gate dielectric pattern disposed on the gate electrode; 
 a channel pattern disposed on the gate dielectric pattern; 
 a source electrode and a drain electrode disposed on the channel pattern and spaced apart from each other; and 
 an insulation pattern disposed between the source electrode and the drain electrode; and 
 
 a first barrier pattern surrounding each of the active components, 
 wherein each of the active components further comprises a second barrier pattern between the insulation pattern and the channel pattern and between the source electrode and the drain electrode. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the first barrier pattern comprises an insulating material having a different etch selectivity from the insulation pattern. 
     
     
       13. The semiconductor device of  claim 11 , wherein sidewalls of the channel patterns that are in contact with the first barrier pattern are substantially coplanar with sidewalls of the source electrodes and the drain electrodes that are in contact with the first barrier pattern. 
     
     
       14. The semiconductor device of  claim 11 , wherein sidewalls of the insulation pattern that are in contact with the first barrier pattern are substantially coplanar with sidewalls of the channel pattern that cross under the source electrode, the drain electrode, and the insulation pattern. 
     
     
       15. The semiconductor device of  claim 11 , wherein the insulation pattern is spaced apart from the channel pattern by the second barrier pattern. 
     
     
       16. The semiconductor device of  claim 11 , wherein each of the active components comprises conductive patterns between the source electrode and the channel pattern and between the drain electrode and the channel pattern. 
     
     
       17. A semiconductor device, comprising:
 an active component disposed on a substrate, wherein the active component comprises:
 a gate electrode disposed on the substrate; 
 a gate dielectric pattern disposed on the gate electrode; 
 a channel pattern disposed on the gate dielectric pattern; 
 a source electrode and a drain electrode disposed on the channel pattern and spaced apart from each other; and 
 an insulation pattern disposed between the source electrode and the drain electrode; and 
 
 a first barrier pattern surrounding each of the active component, 
 wherein sidewalls of the insulation pattern that are in contact with the first barrier pattern substantially align with sidewalls of the channel pattern that are in contact with the first barrier pattern. 
 
     
     
       18. The semiconductor device of  claim 17  further comprising:
 a first dielectric layer disposed between the substrate and the gate electrode; and 
 a first conductor penetrating through the first dielectric layer, wherein the first conductor is electrically connected to the gate electrode. 
 
     
     
       19. The semiconductor device of  claim 18  further comprising:
 a second dielectric layer covering the active component and the first barrier pattern; and 
 second conductors penetrating through the second dielectric layer, wherein the second conductors are electrically connected to the source electrode and the drain electrode. 
 
     
     
       20. The semiconductor device of  claim 17 , wherein the first barrier pattern is in contact with the gate dielectric pattern and the channel pattern.