Molecular layer deposition contact landing protection for 3D NAND

Abstract

Exemplary methods of semiconductor processing may include etching one or more features partially through a dielectric material to expose material from one or more layer pairs formed on a substrate. The methods may include halting the etching prior to penetrating fully through the dielectric material, and prior to exposing material from all layer pairs formed on the substrate. The methods may include forming a layer of carbon-containing material on the exposed material from each of the one or more layer pairs having exposed material. The methods may include etching the one or more features fully through the dielectric material to expose material for each remaining layer pair formed on the substrate.

The invention claimed is: 
     
       1. A semiconductor processing method comprising:
 etching one or more features partially through a dielectric material to expose material from one or more layer pairs in a plurality of layer pairs formed on a substrate; 
 halting the etching prior to penetrating fully through the dielectric material, and prior to exposing material from one or more remaining layer pairs in the plurality of layer pairs formed on the substrate; 
 after halting the etching and exposing the material from the one or more layer pairs, and before exposing the material for the one or more remaining layer pairs, forming a layer of carbon-containing material on the exposed material from each of the one or more layer pairs having exposed material; and 
 after forming the layer of carbon-containing material, etching the one or more features fully through the dielectric material to expose material for each of the one or more remaining layer pairs formed on the substrate. 
 
     
     
       2. The semiconductor processing method of  claim 1 , wherein forming the layer of carbon-containing material comprises one or more cycles of:
 providing a first molecular species that selectively couples with the exposed material formed on the substrate relative to the dielectric material, and 
 providing a second molecular species that selectively couples with the first molecular species. 
 
     
     
       3. The semiconductor processing method of  claim 2 , wherein the first molecular species is characterized by a head group comprising an amine, diamine, diol, or dithiol. 
     
     
       4. The semiconductor processing method of  claim 3 , wherein the second molecular species comprises oxygen. 
     
     
       5. The semiconductor processing method of  claim 2 , wherein forming the layer of carbon-containing material further comprises:
 providing a metal-containing precursor to couple with either of the first molecular species or the second molecular species. 
 
     
     
       6. The semiconductor processing method of  claim 5 , wherein forming the layer of carbon-containing material further comprises:
 alternating delivery of an oxygen-containing material with either of the first molecular species or the second molecular species. 
 
     
     
       7. The semiconductor processing method of  claim 5 , wherein forming the layer of carbon-containing material comprises one or more additional cycles of:
 providing the first molecular species, and 
 providing the second molecular species. 
 
     
     
       8. The semiconductor processing method of  claim 1 , wherein the layer of carbon-containing material is formed to a thickness of greater than or about 5 nm. 
     
     
       9. The semiconductor processing method of  claim 1 , wherein forming the layer of carbon-containing material is performed at a substrate temperature of less than or about 200° C. 
     
     
       10. The semiconductor processing method of  claim 1 , wherein the plurality of layer pairs comprises alternating layers of oxide and silicon nitride, and wherein the silicon nitride overlies the oxide in each layer pair. 
     
     
       11. The semiconductor processing method of  claim 1 , further comprising:
 removing the layer of carbon-containing material from the exposed material from each of the one or more layer pairs having exposed material formed on the substrate, wherein the removing comprises oxidizing the layer of carbon-containing material or performing a thermal anneal. 
 
     
     
       12. A semiconductor processing method comprising:
 etching one or more features partially through a dielectric material to expose silicon nitride from a first set of layer pairs formed on a substrate; 
 halting the etching prior to penetrating fully through the dielectric material, and prior to exposing a second set of layer pairs formed on the substrate under the first set of layer pairs; 
 after halting the etching and exposing the silicon nitride from the first set of layer pairs, and before exposing the second set of layer pairs, forming a layer of carbon-containing material on each region of silicon nitride exposed on the first set of layer pairs; and 
 after forming the layer of carbon-containing material, etching the one or more features fully through the dielectric material to expose silicon nitride from the second set of layer pairs formed on the substrate. 
 
     
     
       13. The semiconductor processing method of  claim 12 , wherein forming the layer of carbon-containing material comprises one or more cycles of:
 providing a first molecular species that selectively couples with the silicon nitride from the first set of layer pairs, and 
 providing a second molecular species that selectively couples with the first molecular species. 
 
     
     
       14. The semiconductor processing method of  claim 13 , wherein the first molecular species comprises an amine head group. 
     
     
       15. The semiconductor processing method of  claim 12 , wherein forming the layer of carbon-containing material is performed at a substrate temperature of less than or about 200° C. 
     
     
       16. The semiconductor processing method of  claim 12 , wherein the layer of carbon-containing material is formed to a thickness of greater than or about 10 nm. 
     
     
       17. The semiconductor processing method of  claim 12 , wherein the first set of layer pairs and the second set of layer pairs comprise alternating layers of oxide and silicon nitride, and wherein the silicon nitride overlies the oxide in each layer pair. 
     
     
       18. The semiconductor processing method of  claim 12 , further comprising:
 removing the layer of carbon-containing material from the region of silicon nitride exposed on the first set of layer pairs formed on the substrate. 
 
     
     
       19. A semiconductor processing method comprising:
 etching one or more features partially through a dielectric material to expose silicon nitride from a first set of layer pairs formed on a substrate, wherein the first set of layer pairs are formed in a staircase structure, and wherein each feature of the one or more features is aligned with a separate layer pair in the first set of layer pairs; 
 halting the etching prior to penetrating fully through the dielectric material, and prior to exposing a second set of layer pairs formed on the substrate under the first set of layer pairs; 
 after halting the etching and exposing the silicon nitride from the first set of layer pairs, and before exposing the second set of layer pairs, forming a layer of carbon-containing material on each region of silicon nitride exposed on the first set of layer pairs; and 
 after forming the layer of carbon-containing material, etching the one or more features fully through the dielectric material to expose silicon nitride from the second set of layer pairs formed on the substrate. 
 
     
     
       20. The semiconductor processing method of  claim 19 , wherein forming the layer of carbon-containing material comprises one or more cycles of:
 providing a first molecular species that selectively couples with the silicon nitride from the first set of layer pairs, and 
 providing a second molecular species that selectively couples with the first molecular species.