Integrated circuit with 3D partitioning

Abstract

Example embodiments relate to integrated circuits with 3D partitioning. One embodiment includes an integrated circuit. The integrated circuit includes a first integrated circuit layer that includes processing cores. The integrated circuit also includes a second integrated circuit layer that includes memory arrays associated with processing cores. Additionally, the integrated circuit includes an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and including memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a first integrated circuit layer comprising a first processing core and a second processing core; 
 a plurality of second integrated circuit layer comprising memory arrays associated with processing cores, wherein the memory arrays comprise local memories of or shared by the first processing core and the second processing core, wherein the plurality of second integrated circuit layers comprises a plurality of cache layers associated with the first processing core or the second processing core, wherein a first cache layer of the plurality of cache layers is associated with a first frequency domain, and wherein a second cache layer of the plurality of cache layers is associated with a second frequency domain; and 
 an intermediate integrated circuit layer interconnected with the first integrated circuit layer and the plurality of second integrated circuit layers, wherein the intermediate integrated circuit layer comprises memory control logic and interface circuitries for managing data exchange between (i) the first processing core and the second processing core and (ii) the memory arrays. 
 
     
     
       2. The integrated circuit according to  claim 1 , wherein the intermediate integrated circuit layer comprises a coherence logic circuitry for managing data consistency across the first processing core and the second processing core. 
     
     
       3. The integrated circuit according to  claim 1 , wherein the intermediate integrated circuit layer further comprises a communication network for interconnecting (i) the first processing core and the second processing core with (ii) one or more external memories. 
     
     
       4. The integrated circuit according to  claim 3 , wherein the intermediate integrated circuit layer comprises interface circuitries for managing the data exchange between (i) the first processing core and the second processing core and (ii) the one or more external memories. 
     
     
       5. The integrated circuit according to  claim 1 , wherein the intermediate integrated circuit layer comprises translation lookaside buffers (TLBs) for memory arrays. 
     
     
       6. The integrated circuit according to  claim 1 , wherein the first processing core comprises a central processing unit (CPU) operating at a frequency range of GHz, and wherein the second processing core comprises a graphics processing unit (GPU) operating at a frequency range of MHz. 
     
     
       7. The integrated circuit according to  claim 6 , wherein the memory arrays of the first cache layer comprise a layer three (L3) cache of the CPU and a layer two (L2) cache of the GPU, and wherein the memory arrays of the second cache layer comprise a layer four (L4) cache of the CPU and a layer three (L3) cache of the GPU. 
     
     
       8. The integrated circuit according to  claim 6 , wherein the CPU operates at a frequency of 2.5 GHz, and wherein the GPU operates at a frequency of 745 MHz. 
     
     
       9. The integrated circuit according to  claim 1 , wherein the second integrated circuit layer further comprises one or more software controlled memories associated with the first processing core and the second processing core. 
     
     
       10. The integrated circuit according to  claim 1 , wherein the memory arrays comprise a system cache. 
     
     
       11. The integrated circuit according to  claim 1 , wherein the memory arrays are three-dimensional (3D) stacked memories. 
     
     
       12. The integrated circuit according to  claim 1 , wherein the first processing core and the second processing core are characterized with different performance or functionality. 
     
     
       13. A system on chip (SoC) comprising:
 a first integrated circuit layer comprising a first processing core and a second processing core; 
 a plurality of second integrated circuit layer comprising memory arrays associated with processing cores, wherein the memory arrays comprise local memories of or shared by the first processing core and the second processing core, wherein the plurality of second integrated circuit layers comprises a plurality of cache layers associated with the first processing core or the second processing core, wherein a first cache layer of the plurality of cache layers is associated with a first frequency domain, and wherein a second cache layer of the plurality of cache layers is associated with a second frequency domain; and 
 an intermediate integrated circuit layer interconnected with the first integrated circuit layer and the plurality of second integrated circuit layers, wherein the intermediate integrated circuit layer comprises memory control logic and interface circuitries for managing data exchange between (i) the first processing core and the second processing core and (ii) the memory arrays. 
 
     
     
       14. The SoC according to  claim 13 , wherein the intermediate integrated circuit layer comprises a coherence logic circuitry for managing data consistency across the first processing core and the second processing core. 
     
     
       15. The SoC according to  claim 13 , wherein the intermediate integrated circuit layer further comprises a communication network for interconnecting (i) the first processing core and the second processing core with (ii) one or more external memories. 
     
     
       16. The SoC according to  claim 15 , wherein the intermediate integrated circuit layer comprises interface circuitries for managing the data exchange between (i) the first processing core and the second processing core and (ii) the one or more external memories. 
     
     
       17. The SoC according to  claim 13 , wherein the intermediate integrated circuit layer comprises translation lookaside buffers (TLBs) for memory arrays. 
     
     
       18. The SoC according to  claim 13 , wherein the first processing core comprises a central processing unit (CPU) operating at a frequency range of GHz, and wherein the second processing core comprises a graphics processing unit (GPU) operating at a frequency range of MHz. 
     
     
       19. The SoC according to  claim 18 , wherein the memory arrays of the first cache layer comprise a layer three (L3) cache of the CPU and a layer two (L2) cache of the GPU, and wherein the memory arrays of the second cache layer comprise a layer four (L4) cache of the CPU and a layer three (L3) cache of the GPU. 
     
     
       20. A system in package (SiP) comprising:
 a first integrated circuit layer comprising a first processing core and a second processing core; 
 a plurality of second integrated circuit layer comprising memory arrays associated with processing cores, wherein the memory arrays comprise local memories of or shared by the first processing core and the second processing core, wherein the plurality of second integrated circuit layers comprises a plurality of cache layers associated with the first processing core or the second processing core, wherein a first cache layer of the plurality of cache layers is associated with a first frequency domain, and wherein a second cache layer of the plurality of cache layers is associated with a second frequency domain; and 
 an intermediate integrated circuit layer interconnected with the first integrated circuit layer and the plurality of second integrated circuit layers, wherein the intermediate integrated circuit layer comprises memory control logic and interface circuitries for managing data exchange between (i) the first processing core and the second processing core and (ii) the memory arrays.