Apparatus and method for dynamic control of microprocessor configuration

Abstract

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

What is claimed is: 
     
       1. A processor comprising:
 a plurality of cores; and 
 one or more interconnects to couple the plurality of cores to memory; 
 wherein in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core, and 
 wherein an interrupt is generated to indicate that the region within the memory is updated with the indication of deactivation of the core. 
 
     
     
       2. The processor of  claim 1 , wherein in response to the interrupt, the region within the memory is read to identify the deactivated core. 
     
     
       3. The processor of  claim 1 , wherein the indication of deactivation of the core is a value of a scalar performance attribute. 
     
     
       4. The processor of  claim 3 , wherein the value of the scalar performance attribute is one of a plurality of values that indicate a corresponding plurality of performance levels of the core. 
     
     
       5. The processor of  claim 3 , wherein the scalar performance attribute is stored in a model-specific register. 
     
     
       6. The processor of  claim 3 , wherein the scalar performance attribute of the core is one of a plurality of attributes of the core that are visible to an operating system scheduler. 
     
     
       7. The processor of  claim 1 , wherein in response to the core configuration command to deactivate the core of the plurality of cores, the core is put into a low power state. 
     
     
       8. The processor of  claim 1 , wherein in response to the core configuration command to deactivate the core of the plurality of cores, one or more interrupt is steered away from the core. 
     
     
       9. The processor of  claim 1 , wherein in response to the core configuration command to deactivate the core of the plurality of cores, one or more system management interrupts to the core are disabled. 
     
     
       10. The processor of  claim 1 , wherein in response to the core configuration command to deactivate the core of the plurality of cores, a frequency of the core is restricted to a value. 
     
     
       11. The processor of  claim 1 , the processor further comprises a power control unit circuitry that causes the region within the memory to be updated with the indication of deactivation of the core. 
     
     
       12. A method comprising:
 coupling a plurality of cores to memory of a processor via one or more interconnects; 
 in response to a core configuration command to deactivate a core of the plurality of cores updating a region within the memory with an indication of deactivation of the core; and 
 generating an interrupt to indicate that the region within the memory is updated with the indication of deactivation of the core. 
 
     
     
       13. The method of  claim 12 , wherein the indication of deactivation of the core is a value of a scalar performance attribute. 
     
     
       14. The method of  claim 12 , further comprising:
 in response to the core configuration command to deactivate the core of the plurality of cores, putting the core into a low power state. 
 
     
     
       15. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, is capable of causing the machine to perform:
 coupling a plurality of cores to memory of a processor via one or more interconnects; 
 in response to a core configuration command to deactivate a core of the plurality of cores updating a region within the memory with an indication of deactivation of the core, and 
 generating an interrupt to indicate that the region within the memory is updated with the indication of deactivation of the core. 
 
     
     
       16. The non-transitory machine-readable medium of  claim 15 , wherein the indication of deactivation of the core is a value of a scalar performance attribute. 
     
     
       17. The non-transitory machine-readable medium of  claim 16 , wherein the scalar performance attribute is stored in a model-specific register. 
     
     
       18. The non-transitory machine-readable medium of  claim 16 , wherein the scalar performance attribute of the core is one of a plurality of attributes of the core that are visible to an operating system scheduler.