Apparatuses and methods for ZQ calibration

Abstract

An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.

What is claimed is: 
     
       1. An apparatus comprising:
 an input/output (I/O) circuit connected to a signal pin, the I/O circuit including a strong driver circuit and a weak driver circuit, wherein the strong driver circuit is stronger than the weak driver circuit; 
 an impedance control (ZQ) calibration circuit connected to a ZQ pin, and configured to perform ZQ calibration using a sweep code or a fixed code, the ZQ pin being connected to a ZQ resistor, the sweep code being updated in a calibration operation related to the ZQ pin, and the fixed code being stored in a register; and 
 a ZQ calibration control circuit connected to the I/O circuit and the ZQ calibration circuit, and configured to:
 generate a ZQ calibration code signal according to ZQ calibration conditions, based on the sweep code or the fixed code, 
 select a driver circuit from among the strong driver circuit and the weak driver circuit based on the ZQ calibration conditions, 
 adjust a termination resistance of the signal pin by providing a ZQ calibration code related to the sweep code to the selected driver circuit, and 
 provide a ZQ calibration code related to the fixed code to an unselected circuit from among the strong driver circuit and the weak driver circuit. 
 
 
     
     
       2. The apparatus of  claim 1 , further comprising a control logic circuit configured to store a mode selection signal and a strength selection signal,
 wherein the ZQ calibration conditions are set based on the mode selection signal, 
 wherein during ZQ calibration of the strong driver circuit, the sweep code or the fixed code is determined based on the mode selection signal, and 
 wherein the strong driver circuit and the weak driver circuit are identified based on the strength selection signal. 
 
     
     
       3. The apparatus of  claim 2 , wherein the I/O circuit further includes:
 a first pull-up driver circuit including a plurality of N-channel metal-oxide semiconductor (NMOS) transistors connected between a power supply voltage line and a signal node connected to the signal pin; 
 a second pull-up driver circuit including a plurality of P-channel MOS (PMOS) transistors connected between the power supply voltage line and the signal node; and 
 a pull-down driver circuit including a plurality of NMOS transistors connected between the signal node and a ground voltage line. 
 
     
     
       4. The apparatus of  claim 3 , wherein the ZQ calibration circuit includes:
 a first pull-up replica circuit, wherein a configuration of the first pull-up replica circuit is same as a configuration of the first pull-up driver circuit, and wherein the first pull-up replica circuit is configured to perform pull-up calibration based on a first fixed code or a first sweep code; 
 a second pull-up replica circuit, wherein a configuration of the second pull-up replica circuit is same as a configuration of the second pull-up driver circuit, and wherein the second pull-up replica circuit is configured to perform the pull-up calibration based on a second fixed code or a second sweep code; and 
 a pull-down replica circuit, wherein a configuration of the pull-down replica circuit is same as a configuration of the pull-down driver circuit, and wherein the pull-down replica circuit is connected to the first pull-up replica circuit and the second pull-up replica circuit and configured to perform pull-down calibration based on a third code. 
 
     
     
       5. The apparatus of  claim 4 , wherein the ZQ calibration control circuit includes:
 a dominant driver detector circuit configured to identify one of the first pull-up driver circuit or the second pull-up driver circuit as the strong driver circuit based on the strength selection signal having a first logic level, and to generate a sweep mode signal; and 
 a first selector configured to, based on the mode selection signal, select one of the sweep mode signal and a fixed mode signal as a code selection signal, and to output the code selection signal, 
 wherein the fixed mode signal is provided from the control logic circuit to set default ZQ calibration. 
 
     
     
       6. The apparatus of  claim 5 , wherein the ZQ calibration control circuit further includes:
 the register, which is configured to store the first fixed code and the second fixed code; and 
 a second selector configured to provide a first ZQ calibration code signal to the first pull-up driver circuit and a second ZQ calibration code signal to the second pull-up driver circuit, 
 wherein the second selector is further configured to:
 based on the code selection signal having the first logic level, output the first sweep code as the first ZQ calibration code signal and the second fixed code as the second ZQ calibration code signal, and 
 based on the code selection signal having a second logic level, output the first fixed code as the first ZQ calibration code signal and the second sweep code as the second ZQ calibration code signal. 
 
 
     
     
       7. The apparatus of  claim 2 , wherein the I/O circuit further includes:
 a pull-up driver circuit including a plurality of N-channel metal-oxide semiconductor (NMOS) transistors connected between a power supply voltage line and a signal node connected to the signal pin; 
 a first pull-down driver circuit including a plurality of P-channel MOS transistors connected between the signal node and a ground voltage line; and 
 a second pull-down driver circuit including a plurality of NMOS transistors connected between the signal node and the ground voltage line. 
 
     
     
       8. The apparatus of  claim 7 , wherein the ZQ calibration circuit includes:
 a first pull-down replica circuit, wherein a configuration of the first pull-down replica circuit is same as a configuration of the first pull-down driver circuit, and wherein the first pull-down replica circuit is configured to perform pull-down calibration based on a third fixed code or a third sweep code; 
 a second pull-down replica circuit, wherein a configuration of the second pull-down replica circuit is same as a configuration of the second pull-down driver circuit, and wherein the second pull-down replica circuit is configured to perform the pull-down calibration based on a fourth fixed code or a fourth sweep code; and 
 a pull-up replica circuit, wherein a configuration of the pull-up replica circuit is same as a configuration of the pull-up driver circuit, and wherein the pull-up replica circuit is connected to the first pull-down replica circuit and the second pull-down replica circuit and configured to perform pull-up calibration based on a first code. 
 
     
     
       9. The apparatus of  claim 8 , wherein the ZQ calibration control circuit includes:
 a dominant driver detector circuit configured to identify one of the first pull-down driver circuit or the second pull-down driver circuit as the strong driver circuit the strength selection signal having a first logic level, and to generate a sweep mode signal; and 
 a first selector configured to, based on the mode selection signal, select one of the sweep mode signal and a fixed mode signal as a code selection signal, and to output the code selection signal, 
 wherein the fixed mode signal is provided from the control logic circuit to set default ZQ calibration. 
 
     
     
       10. The apparatus of  claim 9 , wherein the ZQ calibration control circuit further includes:
 the register, which is configured to store the third fixed code and the fourth fixed code; and 
 a second selector configured to provide a third ZQ calibration code signal to the first pull-down driver circuit and a fourth ZQ calibration code signal to the second pull-down driver circuit, 
 wherein the second selector is further configured to:
 based on the code selection signal having the first logic level, output the third sweep code as the third ZQ calibration code signal and the fourth fixed code as the fourth ZQ calibration code signal, and 
 based on the code selection signal having a second logic level, output the third fixed code as the third ZQ calibration code signal and the fourth sweep code as the fourth ZQ calibration code signal. 
 
 
     
     
       11. The apparatus of  claim 2 , wherein the I/O circuit further includes:
 a first pull-up driver circuit including a plurality of N-channel metal-oxide semiconductor (NMOS) transistors connected between a power supply voltage line and a signal node connected to the signal pin; 
 a second pull-up driver circuit including a plurality of P-channel MOS (PMOS) transistors connected between the power supply voltage line and the signal node; 
 a first pull-down driver circuit including a plurality of PMOS transistors connected between the signal node and a ground voltage line; and 
 a second pull-down driver circuit including a plurality of NMOS transistors connected between the signal node and the ground voltage line. 
 
     
     
       12. An apparatus comprising:
 an input/output (I/O) circuit connected to a signal pin, the I/O circuit including a first driver circuit and a second driver circuit; 
 an impedance control (ZQ) calibration circuit connected to a ZQ pin connected to a ZQ resistor; and 
 a ZQ calibration control circuit connected to the I/O circuit, 
 wherein, based on a strength selection signal set in ZQ calibration conditions having a first logic level, the ZQ calibration control circuit is configured to:
 provide a sweep code to a stronger driver circuit from among the first driver circuit and the second driver circuit, the sweep code being updated by a calibration operation of the ZQ calibration circuit, and 
 provide a fixed code to a weaker driver circuit from among the first driver circuit and the second driver circuit, the fixed code being stored in a register. 
 
 
     
     
       13. The apparatus of  claim 12 , wherein the ZQ calibration control circuit is further configured to provide the sweep code to the weaker driver circuit and the fixed code to the stronger driver circuit based on the strength selection signal having a logic low level. 
     
     
       14. The apparatus of  claim 12 , wherein the ZQ calibration control circuit is further configured to detect a drive strength of the first driver circuit and a drive strength of the second driver circuit at power-up of the apparatus. 
     
     
       15. The apparatus of  claim 12 , wherein the first driver circuit includes a plurality of N-channel metal-oxide semiconductor (NMOS) transistors connected between a power supply voltage line and a signal node connected to the signal pin, and
 wherein the second driver circuit includes a plurality of P-channel MOS (PMOS) transistors connected between the power supply voltage line and the signal node. 
 
     
     
       16. The apparatus of  claim 12 , wherein the first driver circuit includes a plurality of P-channel metal-oxide semiconductor (PMOS) transistors connected between a ground voltage line and a signal node connected to the signal pin, and
 wherein the second driver circuit includes a plurality of N-channel MOS (NMOS) transistors connected between the ground voltage line and the signal node. 
 
     
     
       17. The apparatus of  claim 12 , wherein the first driver circuit includes a plurality of N-channel metal-oxide semiconductor (NMOS) transistors and P-channel MOS (PMOS) transistors connected between a power supply voltage line and a signal node connected to the signal pin, and
 wherein the second driver circuit includes a plurality of PMOS transistors and NMOS transistors connected between the power supply voltage line and the signal node. 
 
     
     
       18. An apparatus comprising:
 an input/output (I/O) circuit connected to a signal pin, the I/O circuit including a first driver circuit having a first drive strength and a second driver circuit having a second drive strength different from the first drive strength; 
 a ZQ calibration control circuit connected to the I/O circuit, 
 wherein, based on the first drive strength being stronger than the second drive strength, the ZQ calibration control circuit is configured to:
 determine a selected driver circuit from among the first driver circuit and the second driver circuit based on a comparison between the first drive strength and the second drive strength, 
 adjust a termination resistance of the signal pin by providing an adjusted ZQ calibration code to the selected driver circuit, and 
 provide a fixed ZQ calibration code to an unselected circuit from among the first driver circuit and the second driver circuit. 
 
 
     
     
       19. The apparatus of  claim 18 , further comprising an impedance control (ZQ) calibration circuit connected to a ZQ pin, and configured to perform a ZQ calibration operation corresponding to the ZQ pin,
 wherein the adjusted ZQ calibration code is updated in the ZQ calibration operation, and the fixed ZQ calibration code is stored in a register. 
 
     
     
       20. The apparatus of  claim 19 , wherein based on the first drive strength being stronger than the second drive strength, the ZQ calibration control circuit is configured to determine the first driver circuit as the selected driver circuit based on a strength selection signal having a first logic level, and to determine the second driver circuit as the selected driver circuit based on the strength selection signal having a second logic level, and
 wherein based on the second drive strength being stronger than the first drive strength, the ZQ calibration control circuit is configured to determine the second driver circuit as the selected driver circuit based on a strength selection signal having the first logic level, and to determine the first driver circuit as the selected driver circuit based on the strength selection signal having the second logic level.