Semiconductor device and method of fabricating the same

Abstract

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

What is claimed is: 
     
       1. A semiconductor package comprising:
 a package substrate including a metal pad; 
 a semiconductor substrate vertically spaced apart from on an upper surface of the package substrate; 
 a conductive pad disposed on a lower surface of on the semiconductor substrate; 
 a protective layer disposed on the lower surface of on the semiconductor substrate and covering a side surface of the conductive pad and a first portion of a lower surface of the conductive pad, the protective layer having a pad opening exposing a second portion of the lower surface of the conductive pad; 
 a pillar pattern disposed in the pad opening and being in contact with the second portion of the lower surface the conductive pad; 
 a solder pattern disposed between the pillar pattern and the metal pad and electrically connected to the metal pad, the solder pattern comprising a solder seed pattern and a solder portion; and 
 a polymer layer being in physical contact with the upper surface of the package substrate, a lower sidewall of the pillar pattern, the protective layer, and at least a portion of a side surface of the semiconductor substrate, 
 wherein the lower sidewall of the pillar pattern is inclined to a top surface of the pillar pattern, 
 wherein a first lower surface of the protective layer on the lower surface of the semiconductor substrate is at a level different from a second lower surface of the protective layer on the first portion of a lower surface of the conductive pad, and 
 wherein the solder pattern comprises: 
 a metal material including at least one of copper and titanium and spaced apart from an edge portion of the pillar pattern; and 
 a solder material including at least one of tin, bismuth, lead, and silver, and in contact with the edge portion of the pillar pattern. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the wherein the protective layer has a stair-stepped structure. 
     
     
       3. The semiconductor package of  claim 1 , wherein the package substrate includes printed circuit board. 
     
     
       4. The semiconductor package of  claim 1 , further comprising:
 an external terminal on a bottom surface of the package substrate, 
 wherein the package substrate further includes an interconnection pattern therein, and 
 wherein the interconnection pattern redistributes the external terminal from the conductive pad. 
 
     
     
       5. The semiconductor package of  claim 1 , wherein an upper portion of the pillar pattern is surrounded by the protective layer, and
 wherein a lower portion of the pillar pattern is surrounded by the polymer layer, and has the lower sidewall. 
 
     
     
       6. The semiconductor package of  claim 5 , wherein a width of the upper portion of pillar pattern surrounded by the protective layer is the same as or less than a width of the lower portion of the pillar pattern surrounded by the polymer layer. 
     
     
       7. The semiconductor package of  claim 6 , wherein the lower portion of the pillar pattern surrounded by the polymer layer has a tapered shape. 
     
     
       8. The semiconductor package of  claim 1 , wherein the solder seed pattern of the solder pattern comprises
 copper; and 
 wherein the solder portion of the solder pattern comprises the solder material. 
 
     
     
       9. The semiconductor package of  claim 1 , wherein sidewalls of the solder pattern do not physically contact the polymer layer. 
     
     
       10. A semiconductor package comprising:
 a package substrate including an interconnection pattern therein; 
 a metal pattern on an upper surface of the package substrate and electrically connected to the interconnection pattern, the metal pattern comprising at least one metal pad; 
 a semiconductor substrate vertically spaced apart from on the upper surface of the package substrate; 
 a conductive pad disposed on a lower surface of on the semiconductor substrate; 
 a protective layer disposed on the lower surface of the semiconductor substrate and covering a side surface of the conductive pad and an edge portion of a lower surface of the conductive pad, the protective layer having a pad opening exposing a center portion of the lower surface of the conductive pad; 
 a connection terminal between the conductive pad and the metal pattern; and 
 a polymer layer disposed between the package substrate and the protective layer, 
 wherein the connection terminal comprises: 
 a pillar pattern disposed in the pad opening and being in contact with the center portion of lower surface the conductive pad; and 
 a solder pattern being in contact with the metal pattern and provided between the metal pattern and the pillar pattern, 
 wherein a width of a lower portion of the pillar pattern is greater than a width of a upper portion of the pillar pattern, 
 and 
 wherein the solder pattern includes:
 a solder seed pattern including copper and spaced apart from an edge portion of a lower surface of the pillar pattern; and 
 a solder material including at least one of tin, bismuth, lead, and silver, and in contact with the edge portion of the lower surface of the pillar pattern. 
 
 
     
     
       11. The semiconductor package of  claim 10 , wherein the upper portion of the pillar pattern is surrounded by the protective layer, and
 wherein the lower portion of the pillar pattern is surrounded by the polymer layer. 
 
     
     
       12. The semiconductor package of  claim 11 , wherein the lower portion of the pillar pattern has an inclined sidewall. 
     
     
       13. The semiconductor package of  claim 10 , wherein the protective layer has:
 a first lower surface on the lower surface of on the semiconductor substrate; and 
 a second lower surface on the edge portion of the lower surface the conductive pad, 
 wherein the first lower surface is provided at a higher level than the second lower surface. 
 
     
     
       14. The semiconductor package of  claim 10 , wherein the polymer layer further extends on a sidewall of the semiconductor substrate. 
     
     
       15. The semiconductor package of  claim 10 , wherein the protective layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and tetraethyl orthosilicate. 
     
     
       16. The semiconductor package of  claim 10 , further comprising
 an external terminal disposed on a bottom surface of the package substrate and being not vertically aligned with the conductive pad, 
 wherein the interconnection pattern redistributes the external terminal from the conductive pad. 
 
     
     
       17. The semiconductor package of  claim 10 , wherein the package substrate includes printed circuit board.