Structure and method for interlevel dielectric layer with regions of differing dielectric constant

Abstract

An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.

The invention claimed is: 
     
       1. A method, comprising:
 forming a plurality of transistors in an integrated circuit; 
 forming a dielectric layer over the transistors; 
 curing a first region of the dielectric layer while shielding a second region of dielectric layer from the curing; 
 forming metal signal lines in the first region; and 
 forming electrodes of a metal-on-metal capacitor in the second region in a same deposition step as the metal signal lines. 
 
     
     
       2. The method of  claim 1 , wherein the curing causes the first region to have a lower dielectric constant than the second region. 
     
     
       3. The method of  claim 1 , wherein the dielectric layer includes SiOCH. 
     
     
       4. The method of  claim 1 , further comprising:
 etching first trenches in the first region of the dielectric layer; 
 etching second trenches in the second region of the dielectric layer; and 
 forming the metal signal lines in the first trenches and the capacitor electrodes in the second trenches by depositing a metal in the first and second trenches. 
 
     
     
       5. The method of  claim 4 , further comprising:
 forming a third trench in the second region; and 
 forming a conductive via in the third trench in contact with and below one of the capacitor electrodes by depositing the metal. 
 
     
     
       6. The method of  claim 5 , further comprising:
 forming a silicon carbide layer over the transistors; and 
 forming the dielectric layer on the silicon carbide layer. 
 
     
     
       7. The method of  claim 6 , wherein the third trench extends through the silicon carbide layer. 
     
     
       8. The method of  claim 7 , further comprising:
 forming a tetraethoxysilane layer on the silicon carbide layer; and 
 forming the dielectric layer on the tetraethoxysilane layer, wherein the third trench extends through the tetraethoxysilane layer and the silicon carbide layer. 
 
     
     
       9. The method of  claim 4 , wherein the first and second trenches extend below the dielectric layer, wherein the metal signal lines and the capacitor electrodes extend below the first dielectric layer. 
     
     
       10. The method of  claim 1 , wherein curing the dielectric layer includes irradiating the dielectric layer with ultraviolet light. 
     
     
       11. The method of  claim 1 , wherein the metal signal lines and the electrodes of the metal-on-metal capacitor include copper. 
     
     
       12. A method, comprising:
 depositing a first interlevel dielectric layer over a semiconductor substrate of an integrated circuit; 
 patterning a mask on the first interlevel dielectric layer; 
 irradiating a first region of the first interlevel dielectric layer exposed by the mask; 
 preventing irradiation of a second region of the first interlevel dielectric layer with the mask; 
 forming first trenches in the first region of the first interlevel dielectric layer; 
 forming second trenches in the second region of the first interlevel dielectric layer; and 
 forming first metal signal lines in the first trenches and first and second electrodes of a capacitor in the second trenches by depositing a metal in the first and second trenches, wherein the first and second electrodes include interleaving finger portions. 
 
     
     
       13. The method of  claim 12 , further comprising:
 depositing a second interlevel dielectric layer over the first interlevel dielectric layer; 
 patterning a second mask on the second interlevel dielectric layer; 
 irradiating a first region of the second interlevel dielectric layer exposed by the second mask; 
 preventing irradiation of a second region of the second interlevel dielectric layer with the second mask; 
 forming first trenches in the first region of the first interlevel dielectric layer; 
 forming second trenches in the second region of the first interlevel dielectric layer; and 
 forming first metal signal lines in the first trenches and first and second electrodes of a capacitor in the second trenches by depositing a metal in the first and second trenches. 
 
     
     
       14. The method of  claim 12 , wherein the first interlevel dielectric layer includes SiOCH. 
     
     
       15. A method, comprising:
 forming a plurality of transistors; 
 forming a first interlevel dielectric layer above the transistors and including a first region having a first dielectric constant a second region having a second dielectric constant greater than the first dielectric constant; 
 forming first metal signal lines in the first region of the first interlevel dielectric layer; and 
 forming a capacitor including a first electrode at least partially in the second region of the first interlevel dielectric layer and a second electrode at least partially in the second region of the first interlevel dielectric layer; 
 forming a second interlevel dielectric layer above the first interlevel dielectric layer and including a first region having the first dielectric constant and a second region having the second dielectric constant higher than the first dielectric constant; and 
 forming second metal lines in the first region of the second interlevel dielectric layer, wherein the first electrode is at least partially in the second region of the second interlevel dielectric layer, wherein the second electrode is at least partially in the second region of the second interlevel dielectric layer. 
 
     
     
       16. The method of  claim 15 , wherein the first region of the first interlevel dielectric layer is more porous than the second region of the first interlevel dielectric layer. 
     
     
       17. The method of  claim 15  wherein the capacitor includes a conductive via extending between the second region of the first dielectric layer and the second region of the second interlevel dielectric layer. 
     
     
       18. The method of  claim 15 , wherein the first signal lines and the first and second electrodes include a same metal. 
     
     
       19. The method of  claim 18 , wherein the metal is copper. 
     
     
       20. The method of  claim 15 , wherein the first interlevel dielectric layer includes SiOCH.