Semiconductor package

Abstract

Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.

What is claimed is: 
     
       1. A semiconductor package, comprising:
 a logic die provided on an interposer substrate; and 
 a memory stack structure provided adjacent to the logic die, 
 wherein the memory stack structure comprises: 
 a buffer die provided on the interposer substrate; and 
 a plurality of memory dies stacked on the buffer die, 
 wherein the buffer die comprises an active layer, the active layer comprising: 
 a first active pattern provided on a first substrate; 
 a first device isolation layer provided on the first substrate and configured to define the first active pattern; and 
 a first gate electrode provided on a channel of the first active pattern, 
 wherein the channel of the first active pattern is positioned higher than an upper surface of the first device isolation layer. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the logic die comprises an active layer, the active layer of the logic die comprising:
 a second active pattern provided on a second substrate; 
 a second device isolation layer provided on the second substrate and configured to define the second active pattern; and 
 a second gate electrode provided on a channel of the second active pattern, 
 wherein the channel of the second active pattern is positioned higher than an upper surface of the second device isolation layer. 
 
     
     
       3. The semiconductor package of  claim 2 , wherein
 the first active pattern comprises a plurality of first active patterns arranged in a first pitch, 
 the second active pattern comprises a plurality of second active patterns arranged in a second pitch, and 
 the first pitch and the second pitch are substantially same. 
 
     
     
       4. The semiconductor package of  claim 1 , wherein the active layer of the buffer die comprises a three-dimensional transistor having the channel that is three-dimensionally structured. 
     
     
       5. The semiconductor package of  claim 1 , wherein
 the logic die comprises a first physical-layer interface region, 
 the buffer die comprises a second physical-layer interface region, 
 the first and second physical-layer interface regions are connected to each other by a data line, and 
 a first transistor of the first physical-layer interface region has a structure substantially same as a structure of a second transistor of the second physical-layer interface region. 
 
     
     
       6. The semiconductor package of  claim 5 , wherein a first pitch between adjacent first active patterns of the first transistor is substantially the same as a second pitch between adjacent second active patterns of the second transistor. 
     
     
       7. The semiconductor package of  claim 5 , wherein the second physical-layer interface region of the buffer die is configured to operate at the same speed as those of the first physical-layer interface region of the logic die. 
     
     
       8. The semiconductor package of  claim 5 , wherein the first transistor of the first physical-layer interface region and the second transistor of the second physical-layer interface region are formed using the same logic process. 
     
     
       9. The semiconductor package of  claim 1 , wherein the memory stack structure further comprises:
 a plurality of first data lines provided between the buffer die and the plurality of memory dies; and 
 a plurality of second data lines provided between the buffer die and the interposer substrate, 
 wherein the number of the first data lines is greater than the number of the second data lines. 
 
     
     
       10. The semiconductor package of  claim 9 , wherein the active layer of the buffer die is configured to allow the plurality of second data lines to have first data rates greater than second data rates of the plurality of first data lines. 
     
     
       11. The semiconductor package of  claim 9 , wherein the number of the first data lines is N times the number of the second data lines, and
 wherein N is 2 to 4. 
 
     
     
       12. The semiconductor package of  claim 1 , wherein the channel has a fin-shaped channel, and
 wherein the first gate electrode surrounds a top surface and both side surfaces of the fin-shaped channel. 
 
     
     
       13. The semiconductor package of  claim 1 , wherein the channel includes a plurality of channels that are spaced apart from each other and sequentially stacked, and
 wherein the first gate electrode surrounds a top surface, both side surfaces and a bottom surface of each of the plurality of channels. 
 
     
     
       14. The semiconductor package of  claim 1 , wherein each of the plurality of memory dies includes data terminals on an active layer of a corresponding memory die of the plurality of memory dies,
 wherein a number of data terminals of each of the plurality of memory dies decreases from a lowermost memory die to an uppermost memory die, 
 wherein the buffer die includes connection terminals between the buffer die and the interposer substrate, and 
 wherein the number of the data terminals of the lowermost memory die is greater than the number of the connection terminals. 
 
     
     
       15. The semiconductor package of  claim 14 , wherein each of the plurality of memory dies further includes through vias passing through the corresponding memory die and connected to the data terminals of the corresponding memory die,
 wherein the number of through vias of each of the plurality of memory dies decreases from the lowermost memory die to the uppermost memory die. 
 
     
     
       16. The semiconductor package of  claim 1 , wherein a planar area of each of the plurality of memory dies decreases from a lowermost memory die to an uppermost memory die. 
     
     
       17. The semiconductor package of  claim 16 , wherein the plurality of memory dies are stacked in a stepwise structure. 
     
     
       18. The semiconductor package of  claim 1 , wherein the plurality of memory dies have substantially the same planar shape and size. 
     
     
       19. The semiconductor package of  claim 1 , wherein the memory stack structure further comprises:
 a plurality of micro-bumps on the active layer of the buffer die; and 
 an under-fill resin layer between the buffer die and the interposer substrate, 
 wherein the plurality of micro-bumps are embedded in the under-fill resin layer. 
 
     
     
       20. A semiconductor package, comprising:
 a logic die provided on an interposer substrate; 
 a buffer die provided on the interposer substrate; and 
 a plurality of memory dies provided on the buffer die, 
 wherein the buffer die comprises an active layer including: 
 a first active pattern provided on a first substrate; 
 a first device isolation layer provided on the first substrate; and 
 a first gate electrode provided on a channel of the first active pattern, and 
 wherein the channel of the first active pattern is positioned higher than an upper surface of the first device isolation layer.