Programmable power balancing in a datacenter

Abstract

A datacenter power management system and method is disclosed. A plurality of computing units are enabled to operate at a second frequency, higher than a first frequency, in response to determining from respective power coefficients for these computing units, that a power level at this higher frequency remains below a power budget.

What is claimed is: 
     
       1. A processor, comprising:
 one or more circuits to cause a plurality of graphics processing units (GPUs) of a baseboard of a server rack, that are operating at a first frequency, to operate at a second frequency, higher than the first frequency, in response to determining, from a plurality of power coefficients, that a baseboard power level at the second frequency remains below a baseboard power budget, wherein each GPU of the plurality of GPUs is associated with a respective power coefficient of the plurality of power coefficients, and wherein each power coefficient of the plurality of power coefficients is a value used to determine, by multiplying the power coefficient with an operating frequency of a respective GPU of the plurality of GPUs, an amount of power consumed by the respective GPU at the operating frequency of the respective GPU. 
 
     
     
       2. The processor of  claim 1 , wherein the one or more circuits are further to cause the plurality of GPUs to operate at a third frequency, lower than the second frequency, in response to determining that the baseboard power level at the second frequency is above the baseboard power budget. 
     
     
       3. The processor of  claim 1 , wherein the one or more circuits are further to cause the plurality of GPUs to operate at a third frequency, higher than the second frequency, in response to determining that the baseboard power level at the third frequency remains below the baseboard power budget. 
     
     
       4. The processor of  claim 1 , wherein the one or more circuits are further to: cause a second plurality of GPUs of a second baseboard of the server rack, that are operating at a third frequency, to operate at a fourth frequency, higher than the third frequency, in response to determining, from a plurality of second power coefficients that a second baseboard power level at the fourth frequency remains below a second baseboard power budget and that a rack power level of the server rack remains below a rack power budget wherein each GPU of the second plurality of GPUs is associated with a respective power coefficient of the plurality of second power coefficients. 
     
     
       5. The processor of  claim 1 , wherein the second frequency increases an operating frequency for a worst case GPU of the plurality of GPUs. 
     
     
       6. The processor of  claim 1 , wherein the one or more circuits cause each GPU of the plurality of GPUs to operate at the second frequency. 
     
     
       7. A method, comprising:
 identifying a plurality of graphics processing units (GPUs) of a baseboard of a server rack operating at a first frequency, wherein each GPU of the plurality of GPUs is associated with a respective power coefficient of a plurality of power coefficients, and wherein each power coefficient of the plurality of power coefficients is a value used to determine, by multiplying the power coefficient with an operating frequency of a respective GPU of the plurality of GPUs, an amount of power consumed by the respective GPU at the operating frequency of the respective GPU, 
 determining, from the plurality of power coefficients, whether a baseboard power level of the baseboard at a second frequency, higher than the first frequency, remains below a baseboard power budget; and 
 causing the plurality of GPUs to operate at a second frequency, higher than the first frequency, in response to determining, from the plurality of power coefficients, that the baseboard power level at the second frequency remains below the baseboard power budget. 
 
     
     
       8. The method of  claim 7 , further comprising:
 determining, from the plurality of power coefficients, that the baseboard power level at a third frequency, higher than the second frequency, remains below the baseboard power budget; and 
 causing the plurality of GPUs to operate at a third frequency, higher than the first frequency, in response to determining, from the plurality of power coefficients, that the baseboard power level at the third frequency remains below the baseboard power budget. 
 
     
     
       9. The method of  claim 8 , further comprising:
 determining that the baseboard power level at the third frequency is within a threshold amount of the baseboard power budget. 
 
     
     
       10. The method of  claim 7 , further comprising:
 determining, from the plurality of power coefficients, that the baseboard power level at a third frequency, higher than the second frequency, exceeds the baseboard power budget; and 
 in response to determining that the baseboard power level at the third frequency exceeds the baseboard power budget, causing the plurality of GPUs to maintain operation at the second frequency. 
 
     
     
       11. The method of  claim 7 , further comprising:
 identifying a second plurality of GPUs of a second baseboard of the server rack operating at a third frequency, wherein each GPU of the second plurality of GPUs is associated with a respective power coefficient of a plurality of second power coefficients; 
 determining, from the plurality of second power coefficients, whether a second baseboard power level at a fourth frequency, higher than the third frequency, remains below a second baseboard power budget; and 
 causing the second plurality of GPUs to operate at the fourth frequency in response to determining from the plurality of second power coefficients, that the second baseboard power level at the fourth frequency remains below the second baseboard power budget. 
 
     
     
       12. The method of  claim 11 , further comprising:
 determining whether a rack power level for the server rack including the plurality of GPUs and the second plurality of GPUs exceeds a rack power budget; and 
 in response to determining that the rack power level exceeds the rack power budget, reducing at least one of the second third frequency or the fourth frequency. 
 
     
     
       13. The method of  claim 12 , further comprising:
 in response to determining that the rack power level exceeds the rack power budget, increasing at least one of the baseboard power level or the second baseboard power level. 
 
     
     
       14. A system, comprising:
 a server rack; 
 a first baseboard including a first plurality of first graphics processing units (GPUs) forming at least a portion of the server rack, wherein each first GPU of the plurality of first GPUs is associated with a respective first power coefficient of a plurality of first power coefficients, and wherein each first power coefficient of the plurality of first power coefficients is a value used to determine, by multiplying the first power coefficient with an operating frequency of a respective first GPU of the plurality of first GPUs, an amount of power consumed by the respective first GPU at the operating frequency of the respective first GPU; 
 a second baseboard including a plurality of second GPUs forming at least a portion of the server rack, wherein each second GPU of the plurality of second GPUs is associated with a respective second power coefficient of a plurality of second power coefficients, and wherein each second power coefficient of the plurality of second power coefficients is a value used to determine, by multiplying the second power coefficient with an operating frequency of a respective second GPU of the plurality of second GPUs, an amount of power consumed by the respective second GPU at the operating frequency of the respective second GPU; and 
 a rack controller including at least one processor and a memory storing instructions that, when executed by the processor, cause the rack controller to:
 cause the first plurality of GPUs to operate at a first frequency, based at least in part on the plurality of first power coefficients, a first baseboard power level of the first baseboard at the first frequency being below a first baseboard power budget; and 
 cause the second plurality of GPUs to operate at a second frequency, based at least in part on the plurality of second power coefficients, a second baseboard power level of the second baseboard at the second frequency being below a second baseboard power budget. 
 
 
     
     
       15. The system of  claim 14 , wherein the memory stores instructions that, when executed by the processor, cause the rack controller to:
 cause the plurality of first GPUs to operate at a third frequency, higher than the first frequency, in response to determining from the plurality of first power coefficients, that the first baseboard power level at the third frequency remains below the first baseboard power budget. 
 
     
     
       16. The system of  claim 14 , wherein the memory stores instructions that, when executed by the processor, cause the rack controller to:
 cause the plurality of first GPUs to operate at a third frequency, less than the first frequency, in response to determining from the plurality of first power coefficients, that a rack power level of the server rack exceeds a rack power budget. 
 
     
     
       17. The system of  claim 14 , wherein the memory stores instructions that, when executed by the processor, cause the rack controller to:
 determine that a rack power level of the server rack, based at least in part on the first baseboard power level and the second baseboard power level, remains below a rack power budget at the first frequency and the second frequency. 
 
     
     
       18. The system of  claim 14 , wherein the memory stores instructions that, when executed by the processor, cause the rack controller to:
 determine that the first baseboard power level at the first frequency is within a threshold amount of the first baseboard power budget. 
 
     
     
       19. The system of  claim 14 , wherein each first GPU of the plurality of first GPUs operates at the first frequency and each second GPU of the plurality of second GPUs operates at the second frequency.